Patents by Inventor Atsushi Hosogane
Atsushi Hosogane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7119362Abstract: In an electric characteristic testing process corresponding to a process of the semiconductor apparatus manufacturing processes, in order to test a large area of the electrode pad of the body to be tested in a lump, an electric characteristic testing is performed by pressing a testing structure provided with electrically independent projections having a number equal to a number of conductor portions to be tested formed on an area to be tested of a body to be tested to the body to be tested.Type: GrantFiled: December 23, 2002Date of Patent: October 10, 2006Assignee: Renesas Technology Corp.Inventors: Ryuji Kono, Makoto Kitano, Hideo Miura, Hiroyuki Ota, Yoshishige Endo, Takeshi Harada, Masatoshi Kanamaru, Teruhisa Akashi, Atsushi Hosogane, Akihiko Ariga, Naoto Ban
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Patent number: 6864568Abstract: A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.Type: GrantFiled: September 24, 2002Date of Patent: March 8, 2005Assignee: Renesas Technology Corp.Inventors: Ryuji Kohno, Hiroya Shimizu, Masatoshi Kanamaru, Atsushi Hosogane, Toshio Miyatake, Hideo Miura, Tatsuya Nagata, Yoshishige Endo, Masaaki Namba, Yuji Wada
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Patent number: 6714030Abstract: A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes.Type: GrantFiled: March 18, 2003Date of Patent: March 30, 2004Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Hideo Miura, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Hideyuki Aoki, Naoto Ban
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Publication number: 20030189439Abstract: A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes.Type: ApplicationFiled: March 18, 2003Publication date: October 9, 2003Inventors: Ryuji Kohno, Hideo Miura, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Hideyuki Aoki, Naoto Ban
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Patent number: 6573112Abstract: Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.Type: GrantFiled: September 11, 2002Date of Patent: June 3, 2003Assignee: Hitachi, Ltd.Inventors: Ryuji Kono, Akihiko Ariga, Hideyuki Aoki, Hiroyuki Ohta, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Shinji Tanaka, Naoto Ban, Hideo Miura
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Patent number: 6566149Abstract: For an inspection tray, a silicon substrate including a beam or a diaphragm, a probe and wiring is used. To highly accurately position a chip to be inspected, a second substrate for alignment is disposed on the substrate. To position the probe having wiring disposed on the first substrate and the electrode pad of the chip to be inspected, a projection or a groove is formed in each of both substrates. Preferably, the projection or groove should be formed by silicon anisotorpic etching to have a (111) crystal surface. As another machining method, dry etching can be used for machining the positioning projection or groove. By using an inductively coupled plasma-reactive ion etching (ICP-RIE) device for the dry etching, a vertical column or groove can be easily machined.Type: GrantFiled: March 16, 2001Date of Patent: May 20, 2003Assignee: Hitachi, Ltd.Inventors: Masatoshi Kanamaru, Atsushi Hosogane, Yoshihige Endou, Ryuji Kouno, Hideo Miura, Shinji Tanaka, Hiroyuki Ohta, Akihiko Ariga, Naoto Ban, Hideyuki Aoki
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Publication number: 20030092206Abstract: In an electric characteristic testing process corresponding to a process of the semiconductor apparatus manufacturing processes, in order to test a large area of the electrode pad of the body to be tested in a lump, an electric characteristic testing is performed by pressing a testing structure provided with electrically independent projections having a number equal to a number of conductor portions to be tested formed on an area to be tested of a body to be tested to the body to be tested.Type: ApplicationFiled: December 23, 2002Publication date: May 15, 2003Inventors: Ryuji Kono, Makoto Kitano, Hideo Miura, Hiroyuki Ota, Yoshishige Endo, Takeshi Harada, Masatoshi Kanamaru, Teruhisa Akashi, Atsushi Hosogane, Akihiko Ariga, Naoto Ban
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Patent number: 6548315Abstract: A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes.Type: GrantFiled: January 29, 2002Date of Patent: April 15, 2003Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Hideo Miura, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Hideyuki Aoki, Naoto Ban
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Patent number: 6531327Abstract: A method for manufacturing a semiconductor device includes forming an integrated circuit on a surface of a wafer and testing electric characteristic of the integrated circuit. The testing includes positioning each of probes of a semiconductor testing equipment and each of electrodes of a tested semiconductor element with each other, and allowing each of the probes to come into contact with each of the electrodes. The semiconductor testing equipment includes a first substrate having a cantilever, the probes being formed on the cantilever of the first substrate, and wires for electrically connecting the probes to electrode pads which are formed on an opposite side of the first substrate to a side on which the probes are formed. Each of the wires has a region arranged on an insulating layer, which is formed on the cantilever, on the opposite side.Type: GrantFiled: February 13, 2002Date of Patent: March 11, 2003Assignee: Hitachi, Ltd.Inventors: Masatoshi Kanamaru, Yoshishige Endo, Atsushi Hosogane, Tatsuya Nagata, Ryuji Kohno, Hideyuki Aoki, Akihiko Ariga
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Publication number: 20030027365Abstract: [Problem] To provide a semiconductor device manufacturing method and a semiconductor device inspection method both of which are capable of efficiently inspecting individual LSI chips separated by cutting, as well as a jig for use in such methods.Type: ApplicationFiled: September 11, 2002Publication date: February 6, 2003Applicant: Hitachi, Ltd.Inventors: Ryuji Kono, Akihiko Ariga, Hideyuki Aoki, Hiroyuki Ohta, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Shinji Tanaka, Naoto Ban, Hideo Miura
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Patent number: 6511857Abstract: In an electric characteristic testing process corresponding to a process of the semiconductor apparatus manufacturing processes, in order to test a large area of the electrode pad of the body to be tested in a lump, an electric characteristic testing is performed by pressing a testing structure provided with electrically independent projections having a number equal to a number of conductor portions to be tested formed on an area to be tested of a body to be tested to the body to be tested.Type: GrantFiled: January 12, 2001Date of Patent: January 28, 2003Assignee: Hitachi, Ltd.Inventors: Ryuji Kono, Makoto Kitano, Hideo Miura, Hiroyuki Ota, Yoshishige Endo, Takeshi Harada, Masatoshi Kanamaru, Teruhisa Akashi, Atsushi Hosogane, Akihiko Ariga, Naoto Ban
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Publication number: 20030015779Abstract: A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.Type: ApplicationFiled: September 24, 2002Publication date: January 23, 2003Inventors: Ryuji Kohno, Hiroya Shimizu, Masatoshi Kanamaru, Atsushi Hosogane, Toshio Miyatake, Hideo Miura, Tatsuya Nagata, Yoshishige Endo, Masaaki Namba, Yuji Wada
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Patent number: 6507204Abstract: The conventional semiconductor element testing equipment is arranged to position each probe accurately and need a burdensome operation for fixing, and includes only a limited number of electrode pads and chips to be tested at a batch. An equipment for testing a semiconductor element is arranged to keep each of electrode pads formed on a semiconductor element to be tested in direct contact with each of probes formed on a first substrate composed of silicon, one of electric connecting substrates disposed in the equipment. On the first substrate, each probe is formed on a cantilever and a wire is routed from a tip of each probe along a tip of the cantilever to the electrode pad formed on an opposite surface to the probe forming surface through an insulating layer.Type: GrantFiled: March 9, 2000Date of Patent: January 14, 2003Assignee: Hitachi, Ltd.Inventors: Masatoshi Kanamaru, Yoshishige Endo, Atsushi Hosogane, Tatsuya Nagata, Ryuji Kohno, Hideyuki Aoki, Akihiko Ariga
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Patent number: 6479305Abstract: Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.Type: GrantFiled: September 15, 1999Date of Patent: November 12, 2002Assignee: Hitachi, Ltd.Inventors: Ryuji Kono, Akihiko Ariga, Hideyuki Aoki, Hiroyuki Ohta, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Shinji Tanaka, Naoto Ban, Hideo Miura
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Patent number: 6465264Abstract: A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.Type: GrantFiled: September 1, 2000Date of Patent: October 15, 2002Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Hiroya Shimizu, Masatoshi Kanamaru, Atsushi Hosogane, Toshio Miyatake, Hideo Miura, Tatsuya Nagata, Yoshishige Endo, Masaaki Namba, Yuji Wada
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Publication number: 20020086451Abstract: A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes.Type: ApplicationFiled: January 29, 2002Publication date: July 4, 2002Inventors: Ryuji Kohno, Hideo Miura, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Hideyuki Aoki, Naoto Ban
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Publication number: 20020072136Abstract: A method for manufacturing a semiconductor device includes forming an integrated circuit on a surface of a wafer and testing electric characteristic of the integrated circuit. The testing includes positioning each of probes of a semiconductor testing equipment and each of electrodes of a tested semiconductor element with each other, and allowing each of the probes to come into contact with each of the electrodes. The semiconductor testing equipment includes a first substrate having a cantilever, the probes being formed on the cantilever of the first substrate, and wires for electrically connecting the probes to electrode pads which are formed on an opposite side of the first substrate to a side on which the probes are formed. Each of the wires has a region arranged on an insulating layer, which is formed on the cantilever, on the opposite side.Type: ApplicationFiled: February 13, 2002Publication date: June 13, 2002Inventors: Masatoshi Kanamaru, Yoshishige Endo, Atsushi Hosogane, Tatsuya Nagata, Ryuji Kohno, Hideyuki Aoki, Akihiko Ariga
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Publication number: 20020064893Abstract: [Problem] To provide a semiconductor device manufacturing method and a semiconductor device inspection method both of which are capable of efficiently inspecting individual LSI chips separated by cutting, as well as a jig for use in such methods. [Means for Resolution] After a multiplicity of LSI chips are cut and separated from one semiconductor wafer, in the step of inspecting LSI chips, a predetermined number N of chips are rearranged and integrated by using a jig for integration which is formed of a material whose coefficient of thermal expansion approximates that of the chips and in which is formed an accommodating portion for rearranging the predetermined number N of chips, and the integrated predetermined number N of chips are subjected to a predetermined inspection process in a subsequent inspection step, whereby inspection efficiency is improved and inspection costs are reduced.Type: ApplicationFiled: September 15, 1999Publication date: May 30, 2002Inventors: RYUJI KONO, AKIHIKO ARIGA, HIDEO MIURA, HIROYUKI OHTA, YOSHISHIGE ENDO, MASATOSHI KANAMARU, ATSUSHI HOSOGANE, SHINJI TANAKA, NAOTO BAN, HIDEYUKI AOKI
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Patent number: 6358762Abstract: A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes.Type: GrantFiled: March 23, 2000Date of Patent: March 19, 2002Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Hideo Miura, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Hideyuki Aoki, Naoto Ban
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Patent number: 5276573Abstract: A slider unit having a reading or reproducing head, with the head being adapted to float over a surface of an information recording disc. The slider unit includes a slider body having a flying height sensor with float surfaces on an underside thereof to generate a lifting force. A piezoelectrically or electrostatically controlled valve layer may be positioned over a vent communicating between an upper surface of the slider, with the vent opening to a recess for generating a negative lift component at an underside of the slider unit. The slider body is made from a ceramic base portion and includes a semiconductive insert portion of, for example, silicon or a photosensitive glass with an adjustment device being formed by utilization of microfabrication techniques such as deposition and etching.Type: GrantFiled: December 2, 1991Date of Patent: January 4, 1994Assignee: Hitachi, Ltd.Inventors: Takeshi Harada, Masatoshi Kanamaru, Atsushi Hosogane, Akiomi Kohno, Kenji Mori