Patents by Inventor Atsushi Kariya

Atsushi Kariya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7842609
    Abstract: A hole is formed in an insulating layer. A semiconductor substrate is heated at a temperature of equal to or more than 330° C. and equal to or less than 400° C. Tungsten-containing gas and at least one of B2H6 gas and SiH4 gas are introduced into a reaction chamber to thereby form a first tungsten layer. Subsequently, at least one of H2 gas and inert gas is introduced into the reaction chamber, the temperature of the semiconductor substrate is raised to equal to or more than 370° C. and equal to or less than 410° C. with 30 or more seconds, and tungsten-containing gas is introduced into the reaction chamber to thereby form a second tungsten layer on the first tungsten layer.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: November 30, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Atsushi Kariya
  • Publication number: 20090275197
    Abstract: A hole is formed in an insulating layer. A semiconductor substrate is heated at a temperature of equal to or more than 330° C. and equal to or less than 400° C. Tungsten-containing gas and at least one of B2H6 gas and SiH4 gas are introduced into a reaction chamber to thereby form a first tungsten layer. Subsequently, at least one of H2 gas and inert gas is introduced into the reaction chamber, the temperature of the semiconductor substrate is raised to equal to or more than 370° C. and equal to or less than 410° C. with 30 or more seconds, and tungsten-containing gas is introduced into the reaction chamber to thereby form a second tungsten layer on the first tungsten layer.
    Type: Application
    Filed: January 9, 2009
    Publication date: November 5, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: ATSUSHI KARIYA
  • Patent number: 6573185
    Abstract: The present method of manufacturing a semiconductor device has a step of forming a metal film on the surface of a group of semiconductor wafers by bringing the internal temperature of a chamber of a film formation device to a film formation temperature at which the metal film is deposited, followed by a step of lowering the temperature of the chamber to a standby temperature at a constant rate and holding the temperature of the chamber at the standby temperature until the film formation for the next group of the semiconductor wafers.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: June 3, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Atsushi Kariya
  • Publication number: 20010024874
    Abstract: The present method of manufacturing a semiconductor device has a step of forming a metal film on the surface of a group of semiconductor wafers by bringing the internal temperature of a chamber of a film formation device to a film formation temperature at which the metal film is deposited, followed by a step of lowering the temperature of the chamber to a standby temperature at a constant rate and holding the temperature of the chamber at the standby temperature until the film formation for the next group of the semiconductor wafers.
    Type: Application
    Filed: March 13, 2001
    Publication date: September 27, 2001
    Applicant: NEC Corporation
    Inventor: Atsushi Kariya
  • Patent number: 6236105
    Abstract: A semiconductor device includes an interlayer insulating film disposed between upper and lower wiring layers, the interlayer insulating film having a two-layered structure including an upper insulating film and a lower insulating film, the upper insulating film is formed in an ozone (O3) concentration higher than that of the lower insulating film. The interlayer insulating film may be composed, for example, of O3 tetra etyl ortho silicate (TEOS) boron phospho silicate glass (BPSG). The semiconductor device makes it possible to have the interlayer insulating film sufficiently planarized by a reflow process, and to prevent precipitation of impurities at a surface of the interlayer insulating film. Alternatively, the interlayer insulating film may have a multi-layered structure including a three or more of insulating films, in which a top insulating film is formed in a higher ozone concentration than that of the other insulating films.
    Type: Grant
    Filed: September 24, 1997
    Date of Patent: May 22, 2001
    Assignee: NEC Corporation
    Inventor: Atsushi Kariya
  • Patent number: 5763329
    Abstract: A method for making a semiconductor device, includes steps of: forming a lower wiring on a semiconductor substrate; forming layer insulation film to cover the lower wiring; coating a surface of the layer insulation film with organic or inorganic SOG to form SOG film; heat-treating the SOG film; etching the SOG film to even a surface of the SOG film; forming an aperture reaching through the SOG film and the layer insulation film to the lower wiring; and filling the aperture with a conductive material to form a through-hole, wherein the coating step with the organic or inorganic SOG is conducted in amine system gas atmosphere.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: June 9, 1998
    Assignee: NEC Corporation
    Inventor: Atsushi Kariya