Patents by Inventor Atsushi Kawamura

Atsushi Kawamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10241909
    Abstract: A write frequency of a non-volatile memory is determined at a fine granularity while suppressing consumption of the volatile memory. When it is determined that a copy of specified data from a specified physical storage area to another physical storage area is to be executed, a controller reads the specified data and specified write frequency information, selects a write destination physical storage area group from a plurality of physical storage area groups based on the specified write frequency information and classification information, selects a write destination physical storage area from the write destination physical storage area group, changes the specified write frequency information, writes the specified data to the write destination physical storage area, writes the changed specified write frequency information to the non-volatile memory, and updates translation information based on the write destination physical storage area group and the write destination physical storage area.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 26, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Kawamura, Masahiro Arai, Kazuhisa Fujimoto
  • Patent number: 10207441
    Abstract: A molding die has a lower holder, an intermediate holder, an upper holder, a lock member, an upper link bar, a lower link bar, a restriction member, and a drive part. A movement of the lock member in a molding die opening direction or a molding die closing direction is restricted by the intermediate holder. The upper link bar has a first retaining groove in which the lock member fits when being located at a molding die closing position. The lower link bar has a second retaining groove in which the lock member fits and a release portion that enables the lock member to be released from the first retaining groove. The restriction member is movable between a restriction position that prevents the lock member from fitting in the second retaining groove and a free position that enables the lock member to fit in the second retaining groove.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: February 19, 2019
    Assignee: DENSO CORPORATION
    Inventors: Atsushi Kawamura, Masato Ichikawa, Masami Gotoh, Tsuyoshi Arai
  • Patent number: 10185624
    Abstract: A first node group including at least three nodes is predefined in a distributed storage system. Each node of the first node group is configured to send data blocks stored in storage devices managed by the node to other nodes belonging to the first node group. A first node is configured to receive data blocks from two or more other nodes in the first node group. The first node is configured to create a redundant code using a combination of data blocks received from the two or more other nodes and store the created redundant code to a storage device different from storage devices holding the data blocks used to create the redundant code. Combinations of data blocks used to create at least two redundant codes in redundant codes created by the first node are different in combination of logical addresses of constituent data blocks.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: January 22, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Hiroaki Akutsu, Shunji Kawamura, Kota Yasunaga, Takahiro Yamamoto, Atsushi Kawamura
  • Publication number: 20190013657
    Abstract: An electrical connection box applied to a wire harness includes a substrate assembly and a housing the substrate assembly. The housing includes a first flexible rib that is extended along an extending direction Z, elastically deformable along a first support direction X, and supports the substrate assembly with respect to one side in the first support direction X, second flexible ribs that are extended along the extending direction Z, elastically deformable along the first support direction X, and supports the substrate assembly with respect to the other side in the first support direction X, and boss portions that are extended along the extending direction Z and position the substrate assembly with respect to the both sides in the first support direction X.
    Type: Application
    Filed: June 19, 2018
    Publication date: January 10, 2019
    Applicants: Yazaki Corporation, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Teppei DOI, Kimihiro ISHII, Tomohiko SAITO, Takayoshi FURUKAWA, Tadashi FUJITA, Yasuhiro YAMAZAKI, Takashi MARUYAMA, Atsushi KAWAMURA, Akihito TSUKAMOTO, Takumi MATSUMOTO
  • Publication number: 20190012260
    Abstract: A flash memory package has a controller and at least one memory including a flash memory. The controller stores received write data in a primary storage area, which is a partial storage area of the memory, sets the unit of storage area including the plurality of physical pages as the unit of collective transfer to perform collective transfer and, when a volume of data accumulated in the primary storage area is equal to or larger than the capacity of one unit of collective transfer of the flash memory, collectively transfers a volume of data corresponding to the capacity of at least one unit of collective transfer from the primary storage area to a secondary storage area, which is a partial storage area of the flash memory.
    Type: Application
    Filed: August 4, 2015
    Publication date: January 10, 2019
    Applicant: HITACHI, LTD.
    Inventors: Atsushi KAWAMURA, Masahiro ARAI, Mitsuhiro OKADA
  • Publication number: 20190004942
    Abstract: A storage device determines whether or not reading target data subjected to a first conversion process is divided and stored into multiple pages. When the data subjected to the first conversion process is stored in one of a plurality of pages, the data is read from the page, and a second conversion process for returning the data to a state before the data is subjected to the first conversion process is executed to the data. When the reading target data is divided and stored into two or more of the plurality of pages, a portion of the data is read from each of the two or more pages in which the portion of the data is stored, the portion of the data is stored in the buffer memory, the data subjected to the first conversion process is restored, and the second conversion process is executed to the restored data.
    Type: Application
    Filed: January 21, 2016
    Publication date: January 3, 2019
    Inventors: Hiroki FUJII, Hideyuki KOSEKI, Atsushi KAWAMURA
  • Publication number: 20180357127
    Abstract: A first node group including at least three nodes is predefined in a distributed storage system. Each node of the first node group is configured to send data blocks stored in storage devices managed by the node to other nodes belonging to the first node group. A first node is configured to receive data blocks from two or more other nodes in the first node group. The first node is configured to create a redundant code using a combination of data blocks received from the two or more other nodes and store the created redundant code to a storage device different from storage devices holding the data blocks used to create the redundant code. Combinations of data blocks used to create at least two redundant codes in redundant codes created by the first node are different in combination of logical addresses of constituent data blocks.
    Type: Application
    Filed: August 22, 2018
    Publication date: December 13, 2018
    Inventors: Hiroaki AKUTSU, Shunji KAWAMURA, Kota YASUNAGA, Takahiro YAMAMOTO, Atsushi KAWAMURA
  • Publication number: 20180339242
    Abstract: A heat treatment furnace device for heat-treating precursor fiber bundles of carbon fibers, having: a heat treatment chamber, in which continuously supplied precursor fiber bundles are treated with hot air, a hot air circulation path, through which hot air from the heat treatment chamber returns to the heat treatment chamber, and a condensation/separation device, into which the hot air flowing through the hot air circulation path is introduced and separated into a condensate and a gas; wherein the condensation/separation device has: a condensation treatment chamber and a condensation unit, which is provided in the condensation treatment chamber and has condensation surfaces on which the condensate is formed and allowed to drip down.
    Type: Application
    Filed: February 24, 2016
    Publication date: November 29, 2018
    Applicant: Mitsubishi Chemical Corporation
    Inventors: Yusuke OKA, Hiroshi INAGAKI, Nobuyuki YAMAMOTO, Atsushi KAWAMURA
  • Patent number: 10132008
    Abstract: A horizontal heat treatment device continuously subjects an untreated continuous flat object to heat treatment while horizontally transferring the untreated object within a heat treatment chamber. Seal chambers are interconnected to the untreated-object loading opening and treated-object unloading opening of the heat treatment chamber. A passage is connected to an opening of each of the seal chambers, the opening located on the side opposite the heat treatment chamber. The untreated-object passage loading opening interconnected to the untreated-object seal chamber loading opening and the treated-object passage unloading opening interconnected to the treated-object seal chamber unloading opening are the untreated-object loading opening and treated-object unloading opening of the heat treatment device. A pair of gas ejection nozzles are provided at upper and lower positions of the passages. The nozzles eject gas in specific directions, and the nozzle openings have a specific shape, a direction, and a length.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: November 20, 2018
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Keishi Mizuno, Tetsu Yasunami, Atsushi Kawamura, Youji Hatanaka, Nobuyuki Yamamoto, Hiromasa Inada
  • Patent number: 10102060
    Abstract: In a storage apparatus including a storage medium including a plurality of pages as a unit of reading and writing data, a first data block including a data block received from a higher-level device is generated, a second data block of a predetermined size including one or more undivided first data blocks is generated, a third data block in which a correction code is added to the second data block is generated, the third data block is stored in a page buffer, and one or more of the third data blocks stored in the page buffer is written in a page, which is a write destination, out of the pages of the storage medium.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 16, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Hideyuki Koseki, Takashi Tsunehiro, Junji Ogawa, Nagamasa Mizushima, Atsushi Kawamura
  • Patent number: 10089033
    Abstract: A storage system according to the present invention has a plurality of flash packages equipped with a deduplication function. When a storage controller transmits a write data and a feature value of write data to a flash package, the flash package compares contents of the write data with data having a same feature value as the feature value of the write data. As a result of the comparison, if there is no corresponding data, the write data is stored in the flash memory, but if there is a corresponding data, the new data will not be stored. Thus, a greater number of data can be stored in the flash memory while preventing deterioration of performance.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: October 2, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Junji Ogawa, Norio Shimozono, Yoshihiro Yoshii, Kazuei Hironaka, Atsushi Kawamura
  • Publication number: 20180253252
    Abstract: A storage system is provided that has a plurality of flash packages and a storage controller that controls read/write processing between a host and the flash packages. When data identical to data written in a second address of a second flash package of the plurality of flash packages is written to a first address of a first flash package of the plurality of flash packages, the storage system may store the second address in the first package in association with the first address, and perform deduplication. When the first flash package stores the second address in association with the first address and a read request for the first address is received from the storage controller, the first flash package may return the second address to the storage controller. In response to receiving the second address, the storage controller may acquire target read data from the second flash package.
    Type: Application
    Filed: September 21, 2016
    Publication date: September 6, 2018
    Applicant: Hitachi, Ltd.
    Inventors: Akira YAMAMOTO, Atsushi KAWAMURA
  • Patent number: 10067828
    Abstract: A memory controller includes an error check correction circuit performing a calculation regarding an error correction code of data, and a processor using the error check correction circuit and write the data with the error correction code to a non-volatile memory (NVM) when writing the data to the NVM, while performing error correction of the data using the error correction code when reading the data from the NVM. The processor counts the number of error bits of the data stored in a block that is a unit of batch-erasure of the data, stores the data in the block with a first error correction code having an error correction ability, and stores the data in the block with a second error correction code having an error correction ability higher than the first error correction code when the number of the error bits is larger than a value.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: September 4, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Nagamasa Mizushima, Atsushi Kawamura, Hideyuki Koseki
  • Patent number: 10061710
    Abstract: The present invention provides a storage device adopting a semiconductor device as a storage media having a nonvolatile property and must be erased for writing data, wherein the device divides and manages a logical storage space provided to a higher level device in logical page units, and manages a virtual address space which is a linear address space to which multiple physical blocks of the semiconductor device are mapped. The storage device uses a page mapping table managing a correspondence between a logical page and an address in the virtual address space, and a virtual address configuration information managing a correspondence between an area in the virtual address space and a physical block, in order to manage the correspondence between the respective logical pages and storage areas of the semiconductor device.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: August 28, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Kawamura, Junji Ogawa
  • Patent number: 10049042
    Abstract: The present invention improves an access performance in an SSD device in which a nonvolatile semiconductor, such as a NAND flash memory, is mounted, or in a storage subsystem having the SSD device built therein, and achieves longer operating life. For this purpose, a plurality of units (logical-physical sizes) for associating a logical address with a physical address is provided in the SSD device or the storage subsystem, and an appropriate logical-physical size is selected in accordance with an I/O size or I/O pattern accessed from a superior device.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: August 14, 2018
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Tsuruya, Atsushi Kawamura, Akifumi Suzuki, Hideyuki Koseki
  • Patent number: 9946616
    Abstract: A storage apparatus includes: a plurality of flash memory devices each including: a plurality of flash memory chips each including a plurality of physical blocks being data erasure units; and a flash controller configured to provide logical storage areas by associating at least one of the plurality of physical blocks with the logical storage areas; and a RAID controller configured to: manage a plurality of virtual drives each including a part of the logical storage areas provided by each of the plurality of flash memory devices; and control the plurality of virtual drives as a RAID group.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: April 17, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Saito, Junji Ogawa, Hiroaki Akutsu, Hideyuki Koseki, Atsushi Kawamura
  • Publication number: 20180067850
    Abstract: A write frequency of a non-volatile memory is determined at a fine granularity while suppressing consumption of the volatile memory. When it is determined that a copy of specified data from a specified physical storage area to another physical storage area is to be executed, a controller reads the specified data and specified write frequency information, selects a write destination physical storage area group from a plurality of physical storage area groups based on the specified write frequency information and classification information, selects a write destination physical storage area from the write destination physical storage area group, changes the specified write frequency information, writes the specified data to the write destination physical storage area, writes the changed specified write frequency information to the non-volatile memory, and updates translation information based on the write destination physical storage area group and the write destination physical storage area.
    Type: Application
    Filed: February 27, 2015
    Publication date: March 8, 2018
    Applicant: HITACHI, LTD.
    Inventors: Atsushi KAWAMURA, Masahiro ARAI, Kazuhisa FUJIMOTO
  • Patent number: 9898539
    Abstract: In a technology for allowing accurate and easy search of a device which satisfies a request of a user from among a large number of devices present at various places, an area ID capable of uniquely identifying a target area of the device is registered in a storage section as information on the device. A device search request from the user includes an area condition for identifying an area in which exertion of an operation by the device is desired by the user as a search condition. A matching process section determines the device to be extracted by comparing the target area identified by the area ID of each device with the area condition included in the device search request.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: February 20, 2018
    Assignee: OMRON Corporation
    Inventors: Atsushi Kawamura, Atsushi Hisano
  • Patent number: 9891989
    Abstract: A control device stores information associating each of a plurality of physical areas with a plurality of logical areas. The control device respectively stores a plurality of first user data included in a first stripe and a first parity data created on the basis thereof in each of the plurality of physical areas, and, in accordance with receiving a write request for updated user data that updates the user data, which is stored in a first physical area, for a first logical area associated with the first physical area, creates a second parity data on the basis of a data group formed using the updated user data and a plurality of second user data that differs from the plurality of first user data.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: February 13, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Kawamura, Akira Yamamoto
  • Publication number: 20180011764
    Abstract: A first node group including at least three nodes is predefined in a distributed storage system. Each node of the first node group is configured to send data blocks stored in storage devices managed by the node to other nodes belonging to the first node group. A first node is configured to receive data blocks from two or more other nodes in the first node group. The first node is configured to create a redundant code using a combination of data blocks received from the two or more other nodes and store the created redundant code to a storage device different from storage devices holding the data blocks used to create the redundant code. Combinations of data blocks used to create at least two redundant codes in redundant codes created by the first node are different in combination of logical addresses of constituent data blocks.
    Type: Application
    Filed: July 28, 2017
    Publication date: January 11, 2018
    Inventors: Hiroaki AKUTSU, Shunji KAWAMURA, Kota YASUNAGA, Takahiro YAMAMOTO, Atsushi KAWAMURA