Patents by Inventor Atsushi Kawamura
Atsushi Kawamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10102060Abstract: In a storage apparatus including a storage medium including a plurality of pages as a unit of reading and writing data, a first data block including a data block received from a higher-level device is generated, a second data block of a predetermined size including one or more undivided first data blocks is generated, a third data block in which a correction code is added to the second data block is generated, the third data block is stored in a page buffer, and one or more of the third data blocks stored in the page buffer is written in a page, which is a write destination, out of the pages of the storage medium.Type: GrantFiled: August 30, 2013Date of Patent: October 16, 2018Assignee: Hitachi, Ltd.Inventors: Hideyuki Koseki, Takashi Tsunehiro, Junji Ogawa, Nagamasa Mizushima, Atsushi Kawamura
-
Patent number: 10089033Abstract: A storage system according to the present invention has a plurality of flash packages equipped with a deduplication function. When a storage controller transmits a write data and a feature value of write data to a flash package, the flash package compares contents of the write data with data having a same feature value as the feature value of the write data. As a result of the comparison, if there is no corresponding data, the write data is stored in the flash memory, but if there is a corresponding data, the new data will not be stored. Thus, a greater number of data can be stored in the flash memory while preventing deterioration of performance.Type: GrantFiled: April 24, 2014Date of Patent: October 2, 2018Assignee: Hitachi, Ltd.Inventors: Akira Yamamoto, Junji Ogawa, Norio Shimozono, Yoshihiro Yoshii, Kazuei Hironaka, Atsushi Kawamura
-
Publication number: 20180253252Abstract: A storage system is provided that has a plurality of flash packages and a storage controller that controls read/write processing between a host and the flash packages. When data identical to data written in a second address of a second flash package of the plurality of flash packages is written to a first address of a first flash package of the plurality of flash packages, the storage system may store the second address in the first package in association with the first address, and perform deduplication. When the first flash package stores the second address in association with the first address and a read request for the first address is received from the storage controller, the first flash package may return the second address to the storage controller. In response to receiving the second address, the storage controller may acquire target read data from the second flash package.Type: ApplicationFiled: September 21, 2016Publication date: September 6, 2018Applicant: Hitachi, Ltd.Inventors: Akira YAMAMOTO, Atsushi KAWAMURA
-
Patent number: 10067828Abstract: A memory controller includes an error check correction circuit performing a calculation regarding an error correction code of data, and a processor using the error check correction circuit and write the data with the error correction code to a non-volatile memory (NVM) when writing the data to the NVM, while performing error correction of the data using the error correction code when reading the data from the NVM. The processor counts the number of error bits of the data stored in a block that is a unit of batch-erasure of the data, stores the data in the block with a first error correction code having an error correction ability, and stores the data in the block with a second error correction code having an error correction ability higher than the first error correction code when the number of the error bits is larger than a value.Type: GrantFiled: October 3, 2014Date of Patent: September 4, 2018Assignee: Hitachi, Ltd.Inventors: Nagamasa Mizushima, Atsushi Kawamura, Hideyuki Koseki
-
Patent number: 10061710Abstract: The present invention provides a storage device adopting a semiconductor device as a storage media having a nonvolatile property and must be erased for writing data, wherein the device divides and manages a logical storage space provided to a higher level device in logical page units, and manages a virtual address space which is a linear address space to which multiple physical blocks of the semiconductor device are mapped. The storage device uses a page mapping table managing a correspondence between a logical page and an address in the virtual address space, and a virtual address configuration information managing a correspondence between an area in the virtual address space and a physical block, in order to manage the correspondence between the respective logical pages and storage areas of the semiconductor device.Type: GrantFiled: January 29, 2014Date of Patent: August 28, 2018Assignee: Hitachi, Ltd.Inventors: Atsushi Kawamura, Junji Ogawa
-
Patent number: 10049042Abstract: The present invention improves an access performance in an SSD device in which a nonvolatile semiconductor, such as a NAND flash memory, is mounted, or in a storage subsystem having the SSD device built therein, and achieves longer operating life. For this purpose, a plurality of units (logical-physical sizes) for associating a logical address with a physical address is provided in the SSD device or the storage subsystem, and an appropriate logical-physical size is selected in accordance with an I/O size or I/O pattern accessed from a superior device.Type: GrantFiled: September 22, 2014Date of Patent: August 14, 2018Assignee: HITACHI, LTD.Inventors: Masahiro Tsuruya, Atsushi Kawamura, Akifumi Suzuki, Hideyuki Koseki
-
Patent number: 9946616Abstract: A storage apparatus includes: a plurality of flash memory devices each including: a plurality of flash memory chips each including a plurality of physical blocks being data erasure units; and a flash controller configured to provide logical storage areas by associating at least one of the plurality of physical blocks with the logical storage areas; and a RAID controller configured to: manage a plurality of virtual drives each including a part of the logical storage areas provided by each of the plurality of flash memory devices; and control the plurality of virtual drives as a RAID group.Type: GrantFiled: January 29, 2014Date of Patent: April 17, 2018Assignee: Hitachi, Ltd.Inventors: Hideo Saito, Junji Ogawa, Hiroaki Akutsu, Hideyuki Koseki, Atsushi Kawamura
-
Publication number: 20180067850Abstract: A write frequency of a non-volatile memory is determined at a fine granularity while suppressing consumption of the volatile memory. When it is determined that a copy of specified data from a specified physical storage area to another physical storage area is to be executed, a controller reads the specified data and specified write frequency information, selects a write destination physical storage area group from a plurality of physical storage area groups based on the specified write frequency information and classification information, selects a write destination physical storage area from the write destination physical storage area group, changes the specified write frequency information, writes the specified data to the write destination physical storage area, writes the changed specified write frequency information to the non-volatile memory, and updates translation information based on the write destination physical storage area group and the write destination physical storage area.Type: ApplicationFiled: February 27, 2015Publication date: March 8, 2018Applicant: HITACHI, LTD.Inventors: Atsushi KAWAMURA, Masahiro ARAI, Kazuhisa FUJIMOTO
-
Patent number: 9898539Abstract: In a technology for allowing accurate and easy search of a device which satisfies a request of a user from among a large number of devices present at various places, an area ID capable of uniquely identifying a target area of the device is registered in a storage section as information on the device. A device search request from the user includes an area condition for identifying an area in which exertion of an operation by the device is desired by the user as a search condition. A matching process section determines the device to be extracted by comparing the target area identified by the area ID of each device with the area condition included in the device search request.Type: GrantFiled: March 8, 2013Date of Patent: February 20, 2018Assignee: OMRON CorporationInventors: Atsushi Kawamura, Atsushi Hisano
-
Patent number: 9891989Abstract: A control device stores information associating each of a plurality of physical areas with a plurality of logical areas. The control device respectively stores a plurality of first user data included in a first stripe and a first parity data created on the basis thereof in each of the plurality of physical areas, and, in accordance with receiving a write request for updated user data that updates the user data, which is stored in a first physical area, for a first logical area associated with the first physical area, creates a second parity data on the basis of a data group formed using the updated user data and a plurality of second user data that differs from the plurality of first user data.Type: GrantFiled: October 11, 2013Date of Patent: February 13, 2018Assignee: Hitachi, Ltd.Inventors: Atsushi Kawamura, Akira Yamamoto
-
Publication number: 20180011764Abstract: A first node group including at least three nodes is predefined in a distributed storage system. Each node of the first node group is configured to send data blocks stored in storage devices managed by the node to other nodes belonging to the first node group. A first node is configured to receive data blocks from two or more other nodes in the first node group. The first node is configured to create a redundant code using a combination of data blocks received from the two or more other nodes and store the created redundant code to a storage device different from storage devices holding the data blocks used to create the redundant code. Combinations of data blocks used to create at least two redundant codes in redundant codes created by the first node are different in combination of logical addresses of constituent data blocks.Type: ApplicationFiled: July 28, 2017Publication date: January 11, 2018Inventors: Hiroaki AKUTSU, Shunji KAWAMURA, Kota YASUNAGA, Takahiro YAMAMOTO, Atsushi KAWAMURA
-
Publication number: 20180001528Abstract: In a molding die, movable die elements are respectively received in die element receiving holes formed in a frame plate. An end surface of the frame plate, which faces a cavity at a location that is other than locations of the die element receiving holes, forms a frame portion compression surface. An end surface of each movable die element, which faces the cavity, forms a split compression surface. Die element drive devices respectively drive the split compression surfaces of the movable die elements. A whole compression plate commonly supports an opposite end part of the frame plate and opposite end parts of the movable die elements, which are opposite from the cavity. When the whole compression plate is moved forward, the whole compression plate integrally drives the frame plate and the movable die elements forward. A whole drive device drives the whole compression plate.Type: ApplicationFiled: January 19, 2016Publication date: January 4, 2018Inventors: Atsushi KAWAMURA, Youhei YOSHIMURA, Tsuyoshi ARAI, Yuka HORI, Mitsuhiro SUZUKI
-
Patent number: 9834869Abstract: To perform a flame-resistant treatment on a precursor fiber strand by sending hot air to a heat treatment chamber (2) through a hot air blowing nozzle (4) in a direction parallel to a running direction of a precursor fiber strand (10). The hot air blowing from the hot air blowing nozzle (4) passes through a porous plate and a rectifying member that satisfy the following conditions (1) to (4), wherein the conditions are set as follows: (1) A/B?4.0; (2) 0.15???0.35; (3) 0?B?d?20; and (4) 80% or more of an area of one opening of the porous plate when causing facing surfaces of the porous plate and the rectifying member to overlap each other is included in one opening of the rectifying member, A indicating a hot air passage distance (mm) of the rectifying member, B indicating a horizontal maximum distance (mm) of one opening of the rectifying member, ? indicating a rate of hole area of the porous plate, and d indicating an equivalent diameter (mm) of the porous plate.Type: GrantFiled: September 14, 2015Date of Patent: December 5, 2017Assignee: Mitsubishi Chemical CorporationInventors: Satoshi Kaji, Nobuyuki Yamamoto, Atsushi Kawamura, Hitoshi Tomobe
-
Publication number: 20170300381Abstract: A memory controller includes an error check correction circuit performing a calculation regarding an error correction code of data, and a processor using the error check correction circuit and write the data with the error correction code to a non-volatile memory (NVM) when writing the data to the NVM, while performing error correction of the data using the error correction code when reading the data from the NVM. The processor counts the number of error bits of the data stored in a block that is a unit of batch-erasure of the data, stores the data in the block with a first error correction code having an error correction ability, and stores the data in the block with a second error correction code having an error correction ability higher than the first error correction code when the number of the error bits is larger than a value.Type: ApplicationFiled: October 3, 2014Publication date: October 19, 2017Inventors: Nagamasa MIZUSHIMA, Atsushi KAWAMURA, Hideyuki KOSEKI
-
Publication number: 20170291339Abstract: A molding die has a lower holder, an intermediate holder, an upper holder, a lock member, an upper link bar, a lower link bar, a restriction member, and a drive part. A movement of the lock member in a molding die opening direction or a molding die closing direction is restricted by the intermediate holder. The upper link bar has a first retaining groove in which the lock member fits when being located at a molding die closing position. The lower link bar has a second retaining groove in which the lock member fits and a release portion that enables the lock member to be released from the first retaining groove. The restriction member is movable between a restriction position that prevents the lock member from fitting in the second retaining groove and a free position that enables the lock member to fit in the second retaining groove.Type: ApplicationFiled: November 12, 2015Publication date: October 12, 2017Applicant: DENSO CORPORATIONInventors: Atsushi KAWAMURA, Masato ICHIKAWA, Masami GOTOH, Tsuyoshi ARAI
-
Publication number: 20170277631Abstract: The present invention improves an access performance in an SSD device in which a nonvolatile semiconductor, such as a NAND flash memory, is mounted, or in a storage subsystem having the SSD device built therein, and achieves longer operating life. For this purpose, a plurality of units (logical-physical sizes) for associating a logical address with a physical address is provided in the SSD device or the storage subsystem, and an appropriate logical-physical size is selected in accordance with an I/O size or I/O pattern accessed from a superior device.Type: ApplicationFiled: September 22, 2014Publication date: September 28, 2017Applicant: HITACHI, LTD.Inventors: Masahiro TSURUYA, Atsushi KAWAMURA, Akifumi SUZUKI, Hideyuki KOSEKI
-
Publication number: 20170192903Abstract: A storage apparatus includes a first storage device and a second storage device, out of logical-physical translation information which associates a logical page and a physical page in the second storage device with each other. Non-compressed logical-physical translation information in the first storage device is assumed to constitute a first tier, compressed logical-physical translation information in the first storage device is assumed to constitute a second tier, and compressed logical-physical translation information in the second storage device is assumed to constitute a third tier. The storage apparatus includes tier management information for managing which logical page is included in logical-physical translation information of which of the first tier, the second tier, and the third tier.Type: ApplicationFiled: October 9, 2014Publication date: July 6, 2017Inventor: Atsushi KAWAMURA
-
Publication number: 20170075620Abstract: A storage system according to the present invention has a plurality of flash packages equipped with a deduplication function. When a storage controller transmits a write data and a feature value of write data to a flash package, the flash package compares contents of the write data with data having a same feature value as the feature value of the write data. As a result of the comparison, if there is no corresponding data, the write data is stored in the flash memory, but if there is a corresponding data, the new data will not be stored. Thus, a greater number of data can be stored in the flash memory while preventing deterioration of performance.Type: ApplicationFiled: April 24, 2014Publication date: March 16, 2017Applicant: HITACHI, LTD.Inventors: Akira YAMAMOTO, Junji OGAWA, Norio SHIMOZONO, Yoshihiro YOSHII, Kazuei HIRONAKA, Atsushi KAWAMURA
-
Patent number: 9585019Abstract: A device management apparatus that mediates between an owner of a device and a user who is not the owner of the device in order to permit the user to use the device, includes a device information storage section in which information on each of a plurality of devices is registered, an acquisition section which acquires a desired condition from a user, and a matching process section which performs matching between the desired condition acquired from the user and the information on each device registered in the device information storage section thereby selecting a device satisfying the desired condition as a target device, generating contract information related to the use of the target device between an owner of the target device and the user, and granting a control right of the target device to the user.Type: GrantFiled: July 31, 2013Date of Patent: February 28, 2017Assignee: OMRON CorporationInventor: Atsushi Kawamura
-
Publication number: 20170010944Abstract: A storage apparatus includes: a plurality of flash memory devices each including: a plurality of flash memory chips each including a plurality of physical blocks being data erasure units; and a flash controller configured to provide logical storage areas by associating at least one of the plurality of physical blocks with the logical storage areas; and a RAID controller configured to: manage a plurality of virtual drives each including a part of the logical storage areas provided by each of the plurality of flash memory devices; and control the plurality of virtual drives as a RAID group.Type: ApplicationFiled: January 29, 2014Publication date: January 12, 2017Applicant: HITACHI, LTD.Inventors: Hideo SAITO, Junji OGAWA, Hiroaki AKUTSU, Hideyuki KOSEKI, Atsushi KAWAMURA