Abstract: An information processing apparatus has strings connected to a first wiring and connected to second wirings. The string has one end connected to the first wiring and includes transistors being connected to each other, gates of which are connected to the second wirings. The transistors include a first transistor and a second transistor. The first transistor is set to a first threshold according to first data, and the second transistor is set to a second threshold according to second data in a complement relationship with the first data. Two second wirings of the second wirings are connected to gates of the first transistor and the second transistor, and one of the two second wirings is set to a potential level corresponding to third data, and another is set to a potential level corresponding to fourth data in a complement relationship with the third data.

Abstract: An information processing device includes a string including a first transistor and a second transistor, and a first wiring line connected to an end of the string. The first transistor has a threshold voltage corresponding to first data. The second transistor has a drain and a source, and a resistance value between the drain and the source corresponds to second data. A current corresponding to a product of the first data and the second data flows through the string.

Abstract: A semiconductor integrated circuit has a digital signal generator that generates a binary signal whose logic transitions at a timing according to a discharge amount of a second wiring which is discharged when multiplication data of first data stored in a memory cell and second data on a first wiring is a first logic; and a transition timing detector that detects a timing at which the logic of the binary signal transitions.

Abstract: A semiconductor storage device includes a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups. Each of word line groups includes a plurality of word lines and each of the blocks includes a plurality of memory cells. The plurality of memory cells of each block are connected to the respective word lines of a corresponding one of the word line groups. The semiconductor storage device includes a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively. Each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.

Abstract: A semiconductor storage device has a plurality of memory cells that are arranged in a first direction and store first data, a plurality of first wiring pairs that are provided corresponding to the plurality of memory cells arranged in the first direction, and supply second data multiplied with the first data, a second wiring pair that is provided corresponding to two memory cells adjacent to each other in the first direction, and outputs multiplication data obtained by multiplying the first data stored in the two memory cells with the corresponding second data on the first wiring pair, and a third wiring pair in which potentials are changed depending on an addition result only when the addition result obtained by adding two multiplication data output to the second wiring pair to each other is not zero.

Abstract: An information processing apparatus has strings connected to a first wiring and connected to second wirings. The string has one end connected to the first wiring and includes transistors being connected to each other, gates of which are connected to the second wirings. The transistors include a first transistor and a second transistor. The first transistor is set to a first threshold according to first data, and the second transistor is set to a second threshold according to second data in a complement relationship with the first data. Two second wirings of the second wirings are connected to gates of the first transistor and the second transistor, and one of the two second wirings is set to a potential level corresponding to third data, and another is set to a potential level corresponding to fourth data in a complement relationship with the third data.

Abstract: A semiconductor memory device according to an embodiment includes a peripheral circuit part supplied with a first voltage, a core circuit part supplied with a second voltage greater than the first voltage, a pre-decoder provided in the peripheral circuit part, input with a signal and outputting a one-hot signal corresponding to the signal, a first wiring provided in the peripheral circuit part, electrically connected to the pre-decoder, and supplied with the one-hot signal, a second wiring provided in the core circuit part, a level shifter provided in the peripheral circuit part, supplied with a first voltage and a second voltage, and transferring the one-hot signal from the first wiring in the peripheral circuit part to the second wiring in the core circuit part, and a memory cell array provided in the core circuit part and operating based on the transferred one-hot signal.

Abstract: According to the embodiment, in a first period, the semiconductor storage device maintains the switch in an ON state. In a second period, the semiconductor storage device performs a first operation, a second operation and a third operation while maintaining the switch in an OFF state. The second period is a period after the first period. The first operation is an operation to supply the first pulse having the first polarity from the first pulse generation circuit to the other end of the first capacitive element. The second operation is an operation to supply the second pulse having the second polarity from the second pulse generation circuit to the other end of the second capacitive element. The third operation is an operation to connect the first bit line to the first data line.

Abstract: Provided is a semiconductor storage device including: a substrate having a substrate surface extending in a first direction and a second direction intersecting the first direction; a plurality of first region memory cells provided in a plurality of layers provided parallel to the substrate surface and in a third direction, the first region memory cells being provided above a rectangular shaped first region provided on the substrate surface, the first region having a first side parallel to the first direction and a second side parallel to the second direction when viewed from the third direction intersecting the first direction and the second direction; a plurality of first region wirings provided between the first region memory cells; a plurality of second region memory cells provided in the layers, the second region memory cells being provided above a rectangular shaped second region having a third side parallel to the first direction and a fourth side parallel to the second direction when viewed from the th

Abstract: A semiconductor integrated circuit has a plurality of memory cells arranged in a first direction and each storing first data, a plurality of first wirings provided to correspond to the plurality of memory cells arranged in the first direction and supplying second data to be multiplied by the first data, and a second wiring pair provided to correspond to the plurality of memory cells arranged in the first direction and that includes one second wiring which is discharged when multiplication data of the first data, stored in each of the plurality of memory cells, and the second data, supplied by the first wiring corresponding to the memory cell, is a first logic; and another second wiring which is discharged when the multiplication data is a second logic.

Abstract: A semiconductor integrated circuit has a digital signal generator that generates a binary signal whose logic transitions at a timing according to a discharge amount of a second wiring which is discharged when multiplication data of first data stored in a memory cell and second data on a first wiring is a first logic; and a transition timing detector that detects a timing at which the logic of the binary signal transitions.

Abstract: A semiconductor memory device of an embodiment includes: a first inverter including a first P-channel and first N-channel transistors; a second inverter including a second P-channel and second N-channel transistors and being cross-connected to the first inverter; a third P-channel transistor; a third N-channel transistor; a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; a sixth wiring; and a controller that drives the first to sixth wirings. When writing second-level data that is at a higher potential level than first-level data into the drain of the second P-channel transistor and the drain of the second N-channel transistor, the controller puts one of the fifth wiring and the sixth wiring into a floating state.

Abstract: A semiconductor memory device according to an embodiment includes a peripheral circuit part supplied with a first voltage, a core circuit part supplied with a second voltage greater than the first voltage, a pre-decoder provided in the peripheral circuit part, input with a signal and outputting a one-hot signal corresponding to the signal, a first wiring provided in the peripheral circuit part, electrically connected to the pre-decoder, and supplied with the one-hot signal, a second wiring provided in the core circuit part, a level shifter provided in the peripheral circuit part, supplied with a first voltage and a second voltage, and transferring the one-hot signal from the first wiring in the peripheral circuit part to the second wiring in the core circuit part, and a memory cell array provided in the core circuit part and operating based on the transferred one-hot signal.

Abstract: A semiconductor storage device has a plurality of memory cells that are arranged in a first direction and store first data, a plurality of first wiring pairs that are provided corresponding to the plurality of memory cells arranged in the first direction, and supply second data multiplied with the first data, a second wiring pair that is provided corresponding to two memory cells adjacent to each other in the first direction, and outputs multiplication data obtained by multiplying the first data stored in the two memory cells with the corresponding second data on the first wiring pair, and a third wiring pair in which potentials are changed depending on an addition result only when the addition result obtained by adding two multiplication data output to the second wiring pair to each other is not zero.

Abstract: Provided is a semiconductor storage device including: a substrate having a substrate surface extending in a first direction and a second direction intersecting the first direction; a plurality of first region memory cells provided in a plurality of layers provided parallel to the substrate surface and in a third direction, the first region memory cells being provided above a rectangular shaped first region provided on the substrate surface, the first region having a first side parallel to the first direction and a second side parallel to the second direction when viewed from the third direction intersecting the first direction and the second direction; a plurality of first region wirings provided between the first region memory cells; a plurality of second region memory cells provided in the layers, the second region memory cells being provided above a rectangular shaped second region having a third side parallel to the first direction and a fourth side parallel to the second direction when viewed from the th

Abstract: According to the embodiment, in a first period, the semiconductor storage device maintains the switch in an ON state. In a second period, the semiconductor storage device performs a first operation, a second operation and a third operation while maintaining the switch in an OFF state. The second period is a period after the first period. The first operation is an operation to supply the first pulse having the first polarity from the first pulse generation circuit to the other end of the first capacitive element. The second operation is an operation to supply the second pulse having the second polarity from the second pulse generation circuit to the other end of the second capacitive element. The third operation is an operation to connect the first bit line to the first data line.

Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring above the first wiring and extending in a second direction, first and second memory cells electrically connected in parallel between the first and second wirings and each including a phase change material, a first insulating film on a side portion of the first cell facing the second cell in the second direction, a third wiring above the second wiring and extending in the second direction, a fourth wiring above the third wiring and extending in the first direction, third and fourth memory cells electrically connected between the third and fourth wirings in parallel and each including a phase change material, and a second insulating film on a side of the third cell facing the fourth cell in the second direction. The first film has a higher thermal insulation capacity than the second film.

Abstract: A semiconductor memory device of an embodiment includes: a first inverter including a first P-channel and first N-channel transistors; a second inverter including a second P-channel and second N-channel transistors and being cross-connected to the first inverter; a third P-channel transistor; a third N-channel transistor; a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; a sixth wiring; and a controller that drives the first to sixth wirings. When writing second-level data that is at a higher potential level than first-level data into the drain of the second P-channel transistor and the drain of the second N-channel transistor, the controller puts one of the fifth wiring and the sixth wiring into a floating state.

Abstract: According to one embodiment, a device includes first lines transmitting a first signals; second lines receiving the first signals; and a first circuit including a first selector coupled to the first lines, a second selector coupled to the second lines, third lines and a fourth lines between the first and second selectors. Each of the third lines stores the second signals, each of the fourth lines stores the third signals. The first circuit counts a first number of second signals equivalent to the corresponding first signal; counts a second number of third signals equivalent to corresponding first signal of the first signals; and couples either the third or the fourth lines to the first and second lines via the first and second selectors, based on a result of comparison between the first and the second numbers.

Abstract: According to an embodiment, a memory device includes a first memory cell and a second memory cell each including a variable resistance element and a switching element, and includes a read and write circuit. The circuit is configured to perform, as a first access, a write operation or a read operation on the first memory cell, and make a second access after the first access. As the second access, data is written into or read from the second memory cell, under a condition based on a type of the first access.