Abstract: An air conditioning management system includes: an air conditioning system including a plurality of air conditioning devices which include an outdoor unit, an indoor unit, and a remote control device each capable of performing wired communication; and a communication terminal. Each air conditioning device of the plurality of air conditioning devices includes a transceiver configured to, in response to receiving a request signal requesting device data, transmit device data of the air conditioning device to another air conditioning device or the communication terminal.

Abstract: An indoor unit of an air-conditioning apparatus includes a main body including a main board that is provided with a control terminal compatible with a plurality of expansion units. The main board is connected to an expansion board provided with at least one expansion terminal that is a connection terminal compliant with the same standard as the control terminal, and is connected to at least one of the plurality of expansion units via the expansion board.

Abstract: An indoor unit of an air-conditioning apparatus includes a main body including a main board that is provided with a control terminal compatible with a plurality of expansion units. The main board is connected to an expansion board provided with at least one expansion terminal that is a connection terminal compliant with the same standard as the control terminal, and is connected to at least one of the plurality of expansion units via the expansion board.

Abstract: A data row of delay time ratio coefficient (hereinafter referred to as DMAG value) is selected from a delay information library (D2) (S4) for every circuit cell in a use condition range of a logic circuit, and the minimum value or/and maximum value of a DMAG value is extracted (S5). The minimum value or/and the maximum delay time is/are calculated for every circuit cell by multiplying the standard delay time to the extracted DMAG value (S6). The above processing is performed for all the circuit cells constituting the logic circuit ((S7): NO), and the data set of the minimum or/and maximum delay time in the use condition range of the logic circuit is/are acquired for every circuit cell (S8).

Abstract: A signal timing analysis method for analyzing timing of a signal propagated along a path including instances. The method includes performing a delay calculation, generating files storing delay information, input slew rate, and output capacitance, performing static timing analysis (STA) based on the delay information, and generating an analysis result. The method includes calculating a delay distribution based on the input slew rate and output capacitance, a probability distribution of a delay time, a probability distribution of a transition time, and a correlation between the delay time and the transition time. The calculation of the delay distribution includes inputting an input slew rate distribution taking into consideration a correlation between output delay and transition distributions for the instance in a preceding stage. The method includes performing STA on the signal propagated along the path based on the analysis result of the STA and delay distribution.

Abstract: A sheet metal is rolled double to form a cylinder having an inner plate 2 and an outer plate 3, and form an overlapped portion 4, with their circumferential end portions 2a and 3a crossed in the circumferential direction. Between the inner plate 2 and the outer plate 3, a plurality of line grooves 5 are formed to extend outward of an outer tube 1, with their tip end portions facing with each other to be apart from each other by a predetermined distance from a peripheral edge of one of the inner plate and outer plate, and these line grooves 5 are arranged in parallel with each other along a longitudinal direction of the outer plate 3. And, at least one portion of the overlapped portion positioned between the neighboring line grooves is joined by welding W.

Abstract: A signal timing analysis method for analyzing timing of a signal propagated along a path including instances. The method includes performing a delay calculation, generating files storing delay information, input slew rate, and output capacitance, performing static timing analysis (STA) based on the delay information, and generating an analysis result. The method includes calculating a delay distribution based on the input slew rate and output capacitance, a probability distribution of a delay time, a probability distribution of a transition time, and a correlation between the delay time and the transition time. The calculation of the delay distribution includes inputting an input slew rate distribution taking into consideration a correlation between output delay and transition distributions for the instance in a preceding stage. The method includes performing STA on the signal propagated along the path based on the analysis result of the STA and delay distribution.

Abstract: A sheet metal is rolled double to form a cylinder having an inner plate 2 and an outer plate 3, and form an overlapped portion 4, with their circumferential end portions 2a and 3a crossed in the circumferential direction. Between the inner plate 2 and the outer plate 3, a plurality of line grooves 5 are formed to extend outward of an outer tube 1, with their tip end portions facing with each other to be apart from each other by a predetermined distance from a peripheral edge of one of the inner plate and outer plate, and these line grooves 5 are arranged in parallel with each other along a longitudinal direction of the outer plate 3. And, at least one portion of the overlapped portion positioned between the neighboring line grooves is joined by welding W.

Abstract: A data row of delay time ratio coefficient (hereinafter referred to as DMAG value) is selected from a delay information library (D2) (S4) for every circuit cell in a use condition range of a logic circuit, and the minimum value or/and maximum value of a DMAG value is extracted (S5). The minimum value or/and the maximum delay time is/are calculated for every circuit cell by multiplying the standard delay time to the extracted DMAG value (S6). The above processing is performed for all the circuit cells constituting the logic circuit ((S7): NO), and the data set of the minimum or/and maximum delay time in the use condition range of the logic circuit is/are acquired for every circuit cell (S8).