Abstract: According to one embodiment, a semiconductor device c includes: a package substrate including a base including a mount portion, and terminals; a semiconductor chip including a first pad to which a ground voltage is supplied, a second pad electrically connected to a first terminal among the terminals, and a semiconductor circuit connected to the first and second pads, the semiconductor chip being provided above the mount portion; and a first capacitor chip including a first capacitor unit provided in a silicon substrate, a first node supplied with the ground voltage, and a second node electrically connected to the second pad, the first capacitor chip being provided above the mount portion.

Abstract: A semiconductor package includes a frame formed of a metal and including multiple grooves formed in a surface, and, a semiconductor chip connected with the surface of the frame. A semiconductor device includes the semiconductor chip, and a base frame formed of copper and bonded to the bottom face of the semiconductor chip. In addition, the semiconductor chip and the base frame are bonded together by surface activation.

Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.

Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.

Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.

Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.

Abstract: To provide a highly reliable semiconductor device which does not suffer from a crack in its package, a semiconductor chip 12 is mounted on a lead frame 11 with a bonding layer 13 between them, and they are sealed with a sealing resin 14. The lead frame 11 has a base member 11a essentially consisting of Cu and an oxide film 11b essentially consisting of an oxide of the base member 11a formed on the base member and having a thickness of about 50 nm or below. By controlling the oxide film 11b to a thickness of about 50 nm or below, an adhesion strength with the sealing resin 14 is improved greatly, so that a package crack does not occur even if a large thermal load is applied in a reflow process for mounting.

Abstract: To provide a highly reliable semiconductor device which does not suffer from a crack in its package, a semiconductor chip 12 is mounted on a lead frame 11 with a bonding layer 13 between them, and they are sealed with a sealing resin 14. The lead frame 11 has a base member 11a essentially consisting of Cu and an oxide film 11b essentially consisting of an oxide of the base member 11a formed on the base member and having a thickness of about 50 nm or below. By controlling the oxide film 11b to a thickness of about 50 nm or below, an adhesion strength with the sealing resin 14 is improved greatly, so that a package crack does not occur even if a large thermal load is applied in a reflow process for mounting.