Patents by Inventor Atsushi Kuwata

Atsushi Kuwata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7698500
    Abstract: A disk array system includes a dedicated cache memory, a first host computer exclusively using the dedicated cache memory, data for a dedicated disk being written to or being read from the dedicated cache memory. The disk array system is connectable to the first host computer and to a second host computer.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: April 13, 2010
    Assignee: NEC Corporation
    Inventor: Atsushi Kuwata
  • Patent number: 7536518
    Abstract: A disc array unit manages a shared memory as a plurality of shared memory blocks, each including a group of cache pages, performs cache control on these cache pages through use of least recently used (LRU) links, and provides an unavailable link as an LRU link to indicate that an area is not available for use as a cache page. When the shared memory block is used not as a cache memory but for another use, the shared memory block is prevented from being used as a cache memory by re-linking all the cache pages belonging to the shared memory block from an LRU link to such unavailable links individually.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: May 19, 2009
    Assignee: NEC Corporation
    Inventor: Atsushi Kuwata
  • Patent number: 7434026
    Abstract: A logical table has a layered structure formed of a higher layer logical table arranged on a memory and a lower layer logical table arranged on a disk and stores where each part of a physical region corresponding to each part of a virtual volume is located, a physical table has a layered structure formed of a higher layer physical table arranged on the memory and a lower layer physical table arranged on the disk and stores a state of assignment of each part of a physical region, and a controller copies a part or all of the lower layer logical table and the lower layer physical table into the memory to conduct management of virtual volume.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: October 7, 2008
    Assignee: NEC Corporation
    Inventor: Atsushi Kuwata
  • Patent number: 7281087
    Abstract: It is desired that the cache hit rate of access from a host (or an application) not be affected by an access pattern of another host (or an application). To achieve this, segment information setting means sets information in a segment information management table based on a setting command from a host (11) or a host (12). Input/output management means identifies to which access group an input/output request from the host (11) or (12) corresponds based on the setting in the segment information management table and the link status of the LRU links corresponding to the cache segments managed in a cache management table and, considering the division sizes allocated to the cache segments, controls discarding data from the cache memory for each cache segment.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: October 9, 2007
    Assignee: NEC Corporation
    Inventor: Atsushi Kuwata
  • Publication number: 20070180189
    Abstract: A disk array system includes a dedicated cache memory, a first host computer exclusively using the dedicated cache memory, data for a dedicated disk being written to or being read from the dedicated cache memory. The disk array system is connectable to the first host computer and to a second host computer.
    Type: Application
    Filed: January 24, 2007
    Publication date: August 2, 2007
    Applicant: NEC CORPORATION
    Inventor: Atsushi Kuwata
  • Publication number: 20060224751
    Abstract: A storage system for use with a node device, includes host modules that access the node device based on an address conversion information. The node device is connectable to the host modules and includes the address conversion information.
    Type: Application
    Filed: March 28, 2006
    Publication date: October 5, 2006
    Applicant: NEC CORPORATION
    Inventor: Atsushi Kuwata
  • Publication number: 20060206663
    Abstract: The disk array device realizing speed-up of cache control by the use of a high-speed throughput bus, which includes a director device having an external interface control unit, a data transfer control unit, a control memory, a processor, a command control unit and a communication buffer, and a shared memory device having a cache data storage memory, a command control unit, a communication buffer, a processor and a cache management memory. The director device and the shared memory device are connected through data transfer control units by a data transfer bus and through command control units by a command communication bus. The data transfer bus and the command communication bus are serial buses whose transfer rate is high.
    Type: Application
    Filed: March 10, 2006
    Publication date: September 14, 2006
    Applicant: NEC CORPORATION
    Inventor: Atsushi Kuwata
  • Patent number: 7032068
    Abstract: A local memory mounted on a host director is provided with a local cache management region for managing a cache page at a steady open state in a cache management region on a shared memory, so that even after data transfer is completed after the use of a cache page on the shared memory subjected to opening processing is finished, the cache page in question is kept open at the steady open state without closing the cache page in question and when an access to the cache page in question is made from the same host director, processing of opening the cache page in question is omitted to improve response performance.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: April 18, 2006
    Assignee: NEC Corporation
    Inventor: Atsushi Kuwata
  • Patent number: 6845426
    Abstract: A disk array controller prevents a cache page conflicts between a plurality of commands issued from the same host. A disk array controller 10 includes host directors 161 and 162, which are provided for hosts 121 and 122, one for each, and which controls I/O requests from the hosts 121 and 122 to execute input/output to or from disk drives 141 and 142, and a shared memory 18 shared by the host directors 161 and 162 and forming a disk cache. When the host 121 issues a plurality of read commands to the same cache page, the host director 161 starts a plurality of data transfers while occupying the cache page during processing of said plurality of read commands.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: January 18, 2005
    Assignee: NEC Corporation
    Inventor: Atsushi Kuwata
  • Publication number: 20040250020
    Abstract: A disc array unit, which manages a shared memory as a plurality of shared memory blocks, each consisting of a group of cache pages, and performs cache control on these cache pages through use of LRU links, provides an unavailable link as an LRU link to indicate that an area is not available for use as a cache page; and, when said shared memory block is used not as a cache memory but for another use, prevents said shared memory block from being used as a cash memory by re-linking all the cache pages belonging to said shared memory block from an LRU link to such unavailable links individually.
    Type: Application
    Filed: June 7, 2004
    Publication date: December 9, 2004
    Applicant: NEC Corporation
    Inventor: Atsushi Kuwata
  • Publication number: 20040133741
    Abstract: A disk array apparatus includes a cache memory for temporarily storing data to be read from or written to disks, and a control unit. The control unit associates data associated with logical addresses with physical addresses, writes the data associated with physical address in the cache memory and processes preferentially for writing the data associated with the physical addresses in the cache memory to the disks.
    Type: Application
    Filed: November 25, 2003
    Publication date: July 8, 2004
    Applicant: NEC CORPORATION
    Inventor: Atsushi Kuwata
  • Publication number: 20040078518
    Abstract: It is desired that the cache hit rate of access from a host (or an application) not be affected by an access pattern of another host (or an application). To achieve this, segment information setting means sets information in a segment information management table based on a setting command from a host (11) or a host (12). Input/output management means identifies to which access group an input/output request from the host (11) or (12) corresponds based on the setting in the segment information management table and the link status of the LRU links corresponding to the cache segments managed in a cache management table and, considering the division sizes allocated to the cache segments, controls discarding data from the cache memory for each cache segment.
    Type: Application
    Filed: October 8, 2003
    Publication date: April 22, 2004
    Applicant: NEC CORPORATION
    Inventor: Atsushi Kuwata
  • Publication number: 20040039875
    Abstract: A logical table has a layered structure formed of a higher layer logical table arranged on a memory and a lower layer logical table arranged on a disk and stores where each part of a physical region corresponding to each part of a virtual volume is located, a physical table has a layered structure formed of a higher layer physical table arranged on the memory and a lower layer physical table arranged on the disk and stores a state of assignment of each part of a physical region, and a controller copies a part or all of the lower layer logical table and the lower layer physical table into the memory to conduct management of virtual volume.
    Type: Application
    Filed: August 7, 2003
    Publication date: February 26, 2004
    Applicant: NEC Corporation
    Inventor: Atsushi Kuwata
  • Publication number: 20030149839
    Abstract: A local memory mounted on a host director is provided with a local cache management region for managing a cache page at a steady open state in a cache management region on a shared memory, so that even after data transfer is completed after the use of a cache page on the shared memory subjected to opening processing is finished, the cache page in question is kept open at the steady open state without closing the cache page in question and when an access to the cache page in question is made from the same host director, processing of opening the cache page in question is omitted to improve response performance.
    Type: Application
    Filed: February 3, 2003
    Publication date: August 7, 2003
    Applicant: NEC Corporation
    Inventor: Atsushi Kuwata
  • Publication number: 20030079087
    Abstract: A cache memory control unit and a cache memory control' method according to the present invention avoids a problem that, when the access frequency of one host is low and the access frequency of another host is high, frequently accessed data pages out less frequently accessed data. A controller includes a function to allocate, in the cache memory, individual cache pages to each access type and to allocate common cache pages regardless of the access type, a function to execute LRU control for each of the individual cache pages and the common cache pages, and a function to load data, which is paged out from the individual cache pages, into the common cache pages. The access type is classified according to a port via which access is made.
    Type: Application
    Filed: October 15, 2002
    Publication date: April 24, 2003
    Applicant: NEC CORPORATION
    Inventor: Atsushi Kuwata
  • Patent number: 6539463
    Abstract: A disk-array apparatus comprises a plurality of disk-medium modules, a first through a fourth memory modules, and a director module connected to a host. The first and the third memory modules are combined with each other so as to serve as a first memory module-pair. The second and the fourth memory modules are combined with each other so as to serve as a second memory module-pair. The director module writes, when a future occurs in the first memory module, fast-write data to the second and the fourth memory modules of the second memory module-pair and appoint two memory modules optionally selected from the second through the fourth memory modules for respectively performing cache control regions.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: March 25, 2003
    Assignee: NEC Corporation
    Inventor: Atsushi Kuwata
  • Publication number: 20020131310
    Abstract: A disk array controller prevents a cache page conflicts between a plurality of commands issued from the same host. A disk array controller 10 includes host directors 161 and 162, which are provided for hosts 121 and 122, one for each, and which controls I/O requests from the hosts 121 and 122 to execute input/output to or from disk drives 141 and 142, and a shared memory 18 shared by the host directors 161 and 162 and forming a disk cache. When the host 121 issues a plurality of read commands to the same cache page, the host director 161 starts a plurality of data transfers while occupying the cache page during processing of said plurality of read commands.
    Type: Application
    Filed: March 13, 2002
    Publication date: September 19, 2002
    Inventor: Atsushi Kuwata
  • Patent number: 6349358
    Abstract: A magnetic disc control apparatus detects a near sequential I/O and pre-reads data from a magnetic disc drive into a cache memory. The control apparatus includes a near sequential I/O processor, which has an I/O history storage table for storing a transfer end address of I/O requested by a host computer, a near sequential I/O identifier for calculating an address difference between the transfer end address read out from this I/O history storage table and the current I/O transfer start address and identifying the I/O as a near sequential I/O if the address difference is within a predetermined value, and a pre-read executor for pre-reading data from the magnetic disc drive to the cache memory when a near sequential I/O is detected.
    Type: Grant
    Filed: August 17, 1999
    Date of Patent: February 19, 2002
    Assignee: NEC Corporation
    Inventor: Atsushi Kuwata
  • Patent number: 6347358
    Abstract: The present invention discloses a disk control unit which improves the use of a cache in a disk unit to increase concurrent access speeds. The disk control unit comprises a plurality of directors each independently controlling an I/O operation between a plurality of hosts and a disk unit, a cache memory connected to the directors and having a plurality of cache areas provided according to the configuration of the disk unit, and a plurality of cache management areas each provided for each of the cache areas for keeping track of whether or not the cache area is used by any of the directors. In addition, the disk control unit has an exclusive control unit which allows each director to reference the cache management area to place the cache area under exclusive control.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: February 12, 2002
    Assignee: NEC Corporation
    Inventor: Atsushi Kuwata
  • Patent number: 6145067
    Abstract: A disk array apparatus includes a plurality of physical disks forming a physical disk group which is logically divided into a plurality of unit areas. The unit areas are combined into a logical disk. This device includes a control section, a logical disk reconfiguration executing section, a P-EXTENT copying means, a read means, a write means, and a double write means. The control section controls an access to the logical disk in accordance with an external request. The logical disk reconfiguration executing section reconfigures the logical disk in accordance with an external request. The P-EXTENT copying means copies data from a unit area as a reconfiguration source to a unit area as a reconfiguration destination when the logical disk is reconfigured. The read means reads out data from a unit area. The write means writes data in a unit area that is not being reconfigured.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: November 7, 2000
    Assignee: NEC Corporation
    Inventor: Atsushi Kuwata