Patents by Inventor Atsushi Mitsuda

Atsushi Mitsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9418245
    Abstract: Included is an encryption processing unit configured to divide and input configuration bits of data to be data processed into a plurality of lines, and to repeatedly execute data conversion processing of data for each line. The encryption processing unit includes an F function execution unit to input data from one line configuring the plurality of lines and generate converted data, an XOR calculation unit to execute an XOR calculation with other lines of data corresponding to the output from the F function, an intermediate data storage register to store intermediate data during the process of generating converted data in the F function execution unit, and an inverse calculation executing unit to calculate input data regarding the F function execution unit on the basis of the data stored in the intermediate storage register.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: August 16, 2016
    Assignee: SONY CORPORATION
    Inventors: Kyoji Shibutani, Toru Akishita, Takanori Isobe, Taizo Shirai, Harunaga Hiwatari, Atsushi Mitsuda
  • Patent number: 9270458
    Abstract: An encryption processing device including an encryption processing part configured to divide configuration bits of data to be data processed into plural lines, and to input, and to repeatedly execute data conversion processing applying a round function to each line of data as a round calculation; and a key scheduling part configured to output round keys to a round calculation executing unit in the encryption processing part. The key scheduling part is a replacement type key scheduling part configured to generate plural round keys or round key configuration data by dividing a secret key stored beforehand into plural parts. The plural round keys are output to a round calculation executing unit sequentially executing in the encryption processing part such that a constant sequence is not repeated. The encryption processing configuration has a high level of security and a high level of resistance to repeated key attacks or other attacks.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: February 23, 2016
    Assignee: Sony Corporation
    Inventors: Kyoji Shibutani, Atsushi Mitsuda, Toru Akishita, Takanori Isobe, Taizo Shirai, Harunaga Hiwatari
  • Patent number: 9083507
    Abstract: A miniaturized non-linear conversion unit is achieved. Included is an encryption processing part configured to divide and input configuration bits of data to be processed into a plurality of lines, and to repeatedly execute a data conversion processing applying a round function as to the data in each line, wherein the encryption processing part includes an F function executing unit configured to input one line of data configuring the plurality of lines, and to generate conversion data, wherein the F function executing unit includes a non-linear conversion processing unit configured to execute a non-linear conversion processing, and wherein the non-linear conversion processing unit includes a repeating structure of a non-linear calculation unit made up from either one NAND or NOR, and either one XOR or XNOR calculation unit, and a bit replacement unit. The miniaturized non-linear conversion unit is achieved by this repeating configuration.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: July 14, 2015
    Assignee: Sony Corporation
    Inventors: Kyoji Shibutani, Toru Akishita, Takanori Isobe, Taizo Shirai, Harunaga Hiwatari, Atsushi Mitsuda
  • Patent number: 8983062
    Abstract: A cryptographic processing unit divides and inputs constituent bits of data to be subjected to data processing to lines, and repeatedly performs a data converting operation using round functions on the data of the respective lines. The cryptographic processing unit inputs n/d-bit data obtained by dividing n-bit data as input data by a division number d to each line, and repeatedly performs a round calculation including a data converting operation using round functions. The n/d-bit data in each line having output data of the round calculations is divided into d/2 sets of data, and the divided data are combined to restructure d sets of n/d-bit data that are different from the output data of the round calculations of the previous stage. The restructured data is set as input data for round calculations of the next stage. The cryptographic processing realizes improved diffusion properties and a high level of security.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventors: Kyoji Shibutani, Toru Akishita, Takanori Isobe, Taizo Shirai, Harunaga Hiwatari, Atsushi Mitsuda
  • Publication number: 20140010364
    Abstract: A cryptographic processing unit divides and inputs constituent bits of data to be subjected to data processing to lines, and repeatedly performs a data converting operation using round functions on the data of the respective lines. The cryptographic processing unit inputs n/d-bit data obtained by dividing n-bit data as input data by a division number d to each line, and repeatedly performs a round calculation including a data converting operation using round functions. The n/d-bit data in each line having output data of the round calculations is divided into d/2 sets of data, and the divided data are combined to restructure d sets of n/d-bit data that are different from the output data of the round calculations of the previous stage. The restructured data is set as input data for round calculations of the next stage. The cryptographic processing realizes improved diffusion properties and a high level of security.
    Type: Application
    Filed: February 20, 2012
    Publication date: January 9, 2014
    Applicant: SONY CORPORATION
    Inventors: Kyoji Shibutani, Toru Akishita, Takanori Isobe, Taizo Shirai, Harunaga Hiwatari, Atsushi Mitsuda
  • Publication number: 20140003603
    Abstract: A miniaturized non-linear conversion unit is achieved. Included is an encryption processing part configured to divide and input configuration bits of data to be processed into a plurality of lines, and to repeatedly execute a data conversion processing applying a round function as to the data in each line, wherein the encryption processing part includes an F function executing unit configured to input one line of data configuring the plurality of lines, and to generate conversion data, wherein the F function executing unit includes a non-linear conversion processing unit configured to execute a non-linear conversion processing, and wherein the non-linear conversion processing unit includes a repeating structure of a non-linear calculation unit made up from either one NAND or NOR, and either one XOR or XNOR calculation unit, and a bit replacement unit. The miniaturized non-linear conversion unit is achieved by this repeating configuration.
    Type: Application
    Filed: February 20, 2012
    Publication date: January 2, 2014
    Applicant: Sony Corporation
    Inventors: Kyoji Shibutani, Toru Akishita, Takanori Isobe, Taizo Shirai, Harunaga Hiwatari, Atsushi Mitsuda
  • Publication number: 20130343546
    Abstract: An encryption processing device including an encryption processing part configured to divide configuration bits of data to be data processed into plural lines, and to input, and to repeatedly execute data conversion processing applying a round function to each line of data as a round calculation; and a key scheduling part configured to output round keys to a round calculation executing unit in the encryption processing part. The key scheduling part is a replacement type key scheduling part configured to generate plural round keys or round key configuration data by dividing a secret key stored beforehand into plural parts. The plural round keys are output to a round calculation executing unit sequentially executing in the encryption processing part such that a constant sequence is not repeated. The encryption processing configuration has a high level of security and a high level of resistance to repeated key attacks or other attacks.
    Type: Application
    Filed: February 20, 2012
    Publication date: December 26, 2013
    Applicant: SONY CORPORATION
    Inventors: Kyoji Shibutani, Atsushi Mitsuda, Toru Akishita, Takanori Isobe, Taizo Shirai, Harunaga Hiwatari
  • Publication number: 20130339753
    Abstract: Miniaturization of an encryption processing configuration is achieved. Included is an encryption processing unit configured to divide and input configuration bits of data to be data processed into a plurality of lines, and to repeatedly execute data conversion processing of data for each line, wherein the encryption processing unit includes an F function execution unit to input data from one line configuring the plurality of lines and generate converted data, an XOR calculation unit to execute an XOR calculation with other lines of data corresponding to the output from the F function, an intermediate data storage register to store intermediate data during the process of generating converted data in the F function execution unit, and an inverse calculation executing unit to calculate input data regarding the F function execution unit on the basis of the data stored in the intermediate storage register.
    Type: Application
    Filed: February 20, 2012
    Publication date: December 19, 2013
    Applicant: SONY CORPORATION
    Inventors: Kyoji Shibutani, Toru Akishita, Takanori Isobe, Taizo Shirai, Harunaga Hiwatari, Atsushi Mitsuda