Abstract: Provided is a system, comprising: a control plane device; and a plurality of user plane devices, wherein the control plane device including: a request receiving unit for receiving a session generating request transmitted by a mobility management device, which has received a connection request from a user terminal; a user plane device selection unit for selecting a user plane device corresponding to the user terminal from the plurality of user plane devices, based on the session generating request; an address acquiring unit for obtaining an IP address assigned to the user terminal based on the session generating request; and a response transmission unit for transmitting a session generating response including the IP address assigned to the user terminal, identification information and IP address of the user plane device selected by the user plane device selection unit, and IP address of a PGW-U.

Abstract: Performing power saving control which can be inherited and standardized easily, and which keeps power devices from having to become larger is made possible. A current In flowing through an electrical path is detected as a voltage Vs by a current detection section, and is outputted as a voltage Vout by an amplifying section. When a level corresponding to the voltage Vout exceeds a limit level, a power limit detection section outputs a power limit detection signal. When a controller receives the power limit detection signal via a detection signal holding section, the controller outputs a throttle control command signal. When a chip set receives the throttle control command signal, the chip set initiates throttle control that lowers the clock frequency of a CPU. The present invention may be applied to laptop personal computers.

Abstract: Performing power saving control which can be inherited and standardized easily, and which keeps power devices from having to become larger is made possible. A current In flowing through an electrical path is detected as a voltage Vs by a current detection section, and is outputted as a voltage Vout by an amplifying section. When a level corresponding to the voltage Vout exceeds a limit level, a power limit detection section outputs a power limit detection signal. When a controller receives the power limit detection signal via a detection signal holding section, the controller outputs a throttle control command signal. When a chip set receives the throttle control command signal, the chip set initiates throttle control that lowers the clock frequency of a CPU. The present invention may be applied to laptop personal computers.