Patents by Inventor Atsushi MORISHIMA
Atsushi MORISHIMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966075Abstract: There is provided an optical member that can achieve a backlight unit excellent in brightness uniformity. The optical member includes: a light guide plate having an end surface that light from a light source enters, an emitting surface from which the entered light is emitted, and a light extraction pattern arranged on a surface opposite to the emitting surface; and a reflective plate bonded to the light guide plate via a double-sided pressure-sensitive adhesive film. An outer edge of the light guide plate is positioned outside an outer edge of the double-sided pressure-sensitive adhesive film, and the outer edge of the double-sided pressure-sensitive adhesive film is positioned outside an outer edge of the light extraction pattern.Type: GrantFiled: March 26, 2021Date of Patent: April 23, 2024Assignee: NITTO DENKO CORPORATIONInventors: Takahiro Yoshikawa, Daisuke Hattori, Ryota Morishima, Atsushi Kishi
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Publication number: 20240101870Abstract: The present invention provides a void-containing layer in which a pressure-sensitive adhesive or an adhesive is less liable to penetrate into voids. A void-containing layer of the present invention, includes: particles chemically bonding to each other, wherein the void-containing layer has a void fraction of 35 vol % or more, the particle is an inorganic-organic composite particle in which an organic group is bonded to an inorganic compound, the organic group includes a R1 group which is a linear or branched alkyl group and a R2 group which is a group containing a carbon-carbon unsaturated bond, and a molar ratio of the R2 group relative to a sum of the R1 group and the R2 group is from 1 to 30 mol %.Type: ApplicationFiled: January 25, 2022Publication date: March 28, 2024Applicant: NITTO DENKO CORPORATIONInventors: Daisuke Hattori, Ryota Morishima, Atsushi Kishi
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Publication number: 20240097441Abstract: A management system includes a plurality of resources configured to be electrically connected to an external power supply, and a management device configured to manage the resources. The management device includes a planning unit and a management unit. The planning unit is configured to determine a power balancing plan of each of the resources by using first information on a use schedule of each of the resources and second information indicating a magnitude of an environmental load in a process of generating electric power to be supplied by the external power supply. The management unit is configured to manage the resources to cause each of the resources to operate according to the power balancing plan or a modified power balancing plan in power balancing of the external power supply.Type: ApplicationFiled: August 3, 2023Publication date: March 21, 2024Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, CHUBU ELECTRIC POWER MIRAIZ CO., INC., CHUBU ELECTRIC POWER CO., INC.Inventors: Yusuke HORII, Eiko Megan UCHIDA, Masashi TANAKA, Masato EHARA, Sachio TOYORA, Tomoya TAKAHASHI, Akinori MORISHIMA, Takuji MATSUBARA, Tohru NAKAMURA, Ryou TAKAHASHI, Kenta ITO, Toshiki SUZUKI, Atsushi MIYASHITA, Takashi OCHIAI
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TRANSMITTING DATA SIGNALS ON SEPARATE LAYERS OF A MEMORY MODULE, AND RELATED METHODS AND APPARATUSES
Publication number: 20210358526Abstract: Apparatuses and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane.Type: ApplicationFiled: July 27, 2021Publication date: November 18, 2021Inventors: Yogesh Sharma, Atsushi Morishima, Yoshihisa Fukushima -
Patent number: 11107507Abstract: Systems, apparatuses, and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane. Each of the DQs may be subject to a single reference layer change, which may occur at or near a DRAM of a memory module (e.g., in the DRAM ball grid array (BGA) area).Type: GrantFiled: June 21, 2019Date of Patent: August 31, 2021Assignee: Micron Technology, Inc.Inventors: Yogesh Sharma, Atsushi Morishima, Yoshihisa Fukushima
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Publication number: 20200402547Abstract: Systems, apparatuses, and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane. Each of the DQs may be subject to a single reference layer change, which may occur at or near a DRAM of a memory module (e.g., in the DRAM ball grid array (BGA) area).Type: ApplicationFiled: June 21, 2019Publication date: December 24, 2020Inventors: Yogesh Sharma, Atsushi Morishima, Yoshihisa Fukushima
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Patent number: 10383298Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.Type: GrantFiled: November 15, 2018Date of Patent: August 20, 2019Assignee: Micron Technology, Inc.Inventor: Atsushi Morishima
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Publication number: 20190098855Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.Type: ApplicationFiled: November 15, 2018Publication date: April 4, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: Atsushi Morishima
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Patent number: 10165683Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.Type: GrantFiled: December 26, 2017Date of Patent: December 25, 2018Assignee: Micron Technology, Inc.Inventor: Atsushi Morishima
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Publication number: 20180192517Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.Type: ApplicationFiled: December 26, 2017Publication date: July 5, 2018Applicant: Micron Technology, Inc.Inventor: Atsushi Morishima
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Patent number: 9888574Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.Type: GrantFiled: January 5, 2017Date of Patent: February 6, 2018Assignee: Micron Technology, Inc.Inventor: Atsushi Morishima
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Publication number: 20110317356Abstract: The present invention is adapted to a memory system that includes: a motherboard and a module board, wherein: the motherboard comprises a module socket mounted on the motherboard; and a plurality of pins two-dimensionally arranged on the module socket, and vertically erected with respect to the motherboard: and the module board comprises a plurality of device chips installed on the module board; and a contact portion mounted on the module board, and including a plurality of through holes two-dimensionally arranged thereon, the contact portion being electrically connected to the device chips: wherein each of the pins is inserted into each of the through holes to connect electrically to the contact portion.Type: ApplicationFiled: June 21, 2011Publication date: December 29, 2011Applicant: ELPIDA MEMORY, INC.Inventors: Takao ONO, Atsushi MORISHIMA