Patents by Inventor Atsushi Morosawa

Atsushi Morosawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230349688
    Abstract: A measurement apparatus for measuring a thickness of a semiconductor wafer includes: an optical system configured to perpendicularly irradiate a sample wafer and a reference wafer with light, and receive interference signals of the light reflected on front and back surfaces of the respective wafers; a signal processor configured to perform frequency analysis of the interference signals received by the optical system to obtain peak positions of a point spread function of the respective wafers; and a calculator configured to calculate a thickness “tsample” of the sample wafer based on the peak position “x” of the sample wafer and the peak position “y” of the reference wafer obtained by the signal processor, and a thickness “treference” of the reference wafer.
    Type: Application
    Filed: March 27, 2023
    Publication date: November 2, 2023
    Inventors: Hiroyuki ITOH, Atsushi MOROSAWA, Keiji ISAMOTO
  • Publication number: 20150085790
    Abstract: Node IDs are stored in an NAT in association with MAC addresses, and bit information indicating whether to reverse a channel allocation rule that is based on whether a node ID is an odd number or an even number is stored in a reverse register. Also, information indicating whether to use each 60G wireless module is stored in a disable register. Then, a CH determination unit allocates a channel to each 60G wireless module based on the NAT, the reverse register, and the disable register. That is, the CH determination unit allocates a channel, for the 60G wireless module to be used, based on whether the node ID is an odd number or an even number and whether to reverse the channel allocation rule that is based on whether the node ID is an odd number or an even number.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 26, 2015
    Inventor: Atsushi Morosawa
  • Publication number: 20150078253
    Abstract: A routing table stores therein an upper unit for 60 G wireless, a lower unit for 60 G wireless, a left unit for 60 G wireless, a right unit for 60 G wireless, or a WLAN unit as a routing destination based on a direction from its own node to a destination node and a distance therebetween. A routing unit routes a packet to the upper unit for 60 G wireless, the lower unit for 60 G wireless, the left unit for 60 G wireless, the right unit for 60 G wireless, or the WLAN unit based on the routing destination retrieved from the routing table through table retrieval.
    Type: Application
    Filed: August 18, 2014
    Publication date: March 19, 2015
    Inventors: Atsushi Morosawa, Takao Matsui
  • Publication number: 20150078382
    Abstract: A node address table (NAT) stores therein a MAC address and a node ID (NID) representing the position of a node in a rack in association with each other for each node, and retrieves NIDs of a destination and its own node based on a destination of a packet and the MAC address of the own node. A destination determination unit determines a routing destination of the packet based on the NIDs of the destination and the own node. A routing unit routes the packet to the routing destination determined by the destination determination unit.
    Type: Application
    Filed: August 20, 2014
    Publication date: March 19, 2015
    Inventors: Atsushi Morosawa, Takao Matsui
  • Publication number: 20150063229
    Abstract: A communication apparatus includes a memory and a processor coupled to the memory. The processor executes a process including: measuring elapsed time of a set standby time; determining whether a communication path to a transmission destination of data is available; transmitting data when the standby time passes in a state in which the communication path is available after it is determined that the communication path is available at the determining; setting, as the standby time, an initial value that is generated using a predetermined time as a unit at start of data transmission at the transmitting, and that is a different value from an initial value of another communication apparatus that communicates with the transmission destination; and resetting, as the standby time, a resetting value that is generated using the predetermined time as a unit when the standby time has passed.
    Type: Application
    Filed: June 30, 2014
    Publication date: March 5, 2015
    Inventor: Atsushi Morosawa
  • Publication number: 20140035633
    Abstract: On a transmission path connecting a first semiconductor integrated circuit that is started by a system management apparatus and a second semiconductor integrated circuit that is not started by the system management apparatus, when connection of the first semiconductor integrated circuit to the second semiconductor integrated circuit is detected, after being turned to a first signal state for detecting a valid lane, each lane on the transmission path is turned to a second signal state corresponding to each bit of initial setting code. In the second semiconductor integrated circuit, the first and second signal states are detected for each lane of the transmission path. Based on the detected signal state, after detecting the first signal state, the second signal state is detected and each bit value of the initial setting code is decoded. Based on the decoded initial setting code, an initialization process is executed.
    Type: Application
    Filed: October 7, 2013
    Publication date: February 6, 2014
    Applicant: Fujitsu Limited
    Inventors: Junji ICHIMIYA, TAKESHI OWAKI, Daisuke ITO, Atsushi MOROSAWA, NORIHIKO FUKUZUMI
  • Publication number: 20130343382
    Abstract: A relay device includes a first determining unit, a first sending unit, a receiving unit, a setting unit, a second determining unit, and a second sending unit. When the first determining unit determines that the relay device is a parent node, the first sending unit sends a set value stored in a storing unit to all the other relay devices to which the relay device is connected. When the first determining unit determines that the relay device is not the parent node, the receiving unit receives the set value. The setting unit sets the set value received by the receiving unit in the storing unit. When the second determining unit determines that the received set value has not been sent to the other relay devices, the second sending unit sends the received set value to the other relay devices to which the relay device is connected.
    Type: Application
    Filed: August 26, 2013
    Publication date: December 26, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi OWAKI, Daisuke Ito, Junji Ichimiya, Atsushi Morosawa, Norihiko Fukuzumi
  • Patent number: 8607103
    Abstract: A transmission/reception device includes a transmission device that divides a plurality of connection lines into a plurality of groups, determines corresponding connection lines in the plurality of groups, determines a correspondence between test pattern and the connection line, and outputs the test pattern to the plurality of connection lines based on the correspondence between the test pattern and the connection line, and a reception device that receives the test pattern from the transmission device, compares bits in a same position of the test pattern received through a corresponding connection line in the plurality of groups based on the correspondence between the test pattern and the connection line, and generates erroneous connection line information indicating an erroneous connection line as a connection line in which an error has occurred in the plurality of connection lines based on a result of the comparison.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: December 10, 2013
    Assignee: Fujitsu Limited
    Inventors: Takeshi Owaki, Takaharu Ishizuka, Susumu Akiu, Atsushi Morosawa
  • Patent number: 8458551
    Abstract: A verification device includes a data verifying unit that verifies whether data in a packet has an error using a first or a second verification mode, a packet generating unit that generates a packet in accordance with a first packet generation mode or a second packet generation mode respectively corresponding to the first and the second verification modes, a failure monitoring unit that monitors a failure of a transmission line that requires a switching of the verification mode, a switching packet transmitting unit that transmits to a destination device, a switching packet for informing the switching of the verification mode used by the data verifying unit when the failure monitoring unit detects a failure or a removal of a failure, a generation mode switching unit that switches the generation mode, and a verification mode switching unit that switches the verification mode to the one informed by the switching packet.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: June 4, 2013
    Assignee: Fujitsu Limited
    Inventors: Takeshi Owaki, Takaharu Ishizuka, Toshikazu Ueki, Takashi Yamamoto, Atsushi Morosawa
  • Patent number: 8391184
    Abstract: A method of updating a routing table includes: receiving, from an issue-source node, a write packet that includes update data for updating the routing table; attempting to recognize, based upon contents of the write packet, a partition in which the issue-source node is included; determining whether to permit updating the routing table based upon (1) whether the partition including the source node is recognized and (2) whether port information and partition information in the update data are stored in the routing table; and updating the routing table when updating is permitted.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: March 5, 2013
    Assignee: Fujitsu Limited
    Inventors: Susumu Akiu, Takaharu Ishizuka, Takeshi Owaki, Atsushi Morosawa
  • Publication number: 20120236843
    Abstract: A method of switching internal settings in an information processing apparatus including a plurality of processors, a crossbar switch connected to the plurality of processors and having a first routing table and a second routing table used for routing between the plurality of processors and an external apparatus, and a management unit managing the plurality of processors. The method includes performing, by the processors, data communication with the external apparatus using the first routing table, updating, by the management unit, configuration information in the second routing table when a configuration of the information processing apparatus is changed, instructing, by the management unit, any one of the processors to switch the updated second routing table and the first routing table, and switching, by the processor instructed by the management unit, a routing table to be used for the data communication from the first routing table to the updated second routing table.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 20, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Atsushi Morosawa, Takaharu Ishizuka, Takeshi Owaki, Susumu Akiu
  • Patent number: 8181064
    Abstract: A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in a firmware hub instructs the northbridge to inhibit an external instruction. In addition, the firmware saves the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU saved on the memory to all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: May 15, 2012
    Assignee: Fujitsu Limited
    Inventors: Takeshi Owaki, Takaharu Ishizuka, Toshikazu Ueki, Makoto Hataida, Yuka Hosokawa, Atsushi Morosawa, Takashi Yamamoto, Daisuke Itou
  • Publication number: 20110320885
    Abstract: A transmission/reception device includes a transmission device that divides a plurality of connection lines into a plurality of groups, determines corresponding connection lines in the plurality of groups, determines a correspondence between test pattern and the connection line, and outputs the test pattern to the plurality of connection lines based on the correspondence between the test pattern and the connection line, and a reception device that receives the test pattern from the transmission device, compares bits in a same position of the test pattern received through a corresponding connection line in the plurality of groups based on the correspondence between the test pattern and the connection line, and generates erroneous connection line information indicating an erroneous connection line as a connection line in which an error has occurred in the plurality of connection lines based on a result of the comparison.
    Type: Application
    Filed: September 2, 2011
    Publication date: December 29, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi OWAKI, Takaharu Ishizuka, Susumu Akiu, Atsushi Morosawa
  • Patent number: 8078920
    Abstract: An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: December 13, 2011
    Assignee: Fujitsu Limited
    Inventors: Atsushi Morosawa, Takaharu Ishizuka, Toshikazu Ueki, Makoto Hataida, Yuka Hosokawa, Takeshi Owaki, Takashi Yamamoto, Daisuke Itou
  • Publication number: 20110047431
    Abstract: A verification device includes a data verifying unit that verifies whether data in a packet has an error using a first or a second verification mode, a packet generating unit that generates a packet in accordance with a first packet generation mode or a second packet generation mode respectively corresponding to the first and the second verification modes, a failure monitoring unit that monitors a failure of a transmission line that requires a switching of the verification mode, a switching packet transmitting unit that transmits to a destination device, a switching packet for informing the switching of the verification mode used by the data verifying unit when the failure monitoring unit detects a failure or a removal of a failure, a generation mode switching unit that switches the generation mode, and a verification mode switching unit that switches the verification mode to the one informed by the switching packet.
    Type: Application
    Filed: November 2, 2010
    Publication date: February 24, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Owaki, Takaharu Ishizuka, Toshikazu Ueki, Takashi Yamamoto, Atsushi Morosawa
  • Publication number: 20110026524
    Abstract: A method of updating a routing table includes: receiving, from an issue-source node, a write packet that includes update data for updating the routing table; attempting to recognize, based upon contents of the write packet, a partition in which the issue-source node is included; determining whether to permit updating the routing table based upon (1) whether the partition including the source node is recognized and (2) whether port information and partition information in the update data are stored in the routing table; and updating the routing table when updating is permitted.
    Type: Application
    Filed: July 29, 2010
    Publication date: February 3, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Susumu Akiu, Takaharu Ishizuka, Takeshi Owaki, Atsushi Morosawa
  • Patent number: 7835010
    Abstract: A tunable light source 10 for varying emission wavelength periodically and an optical interferometer are used. A reflector is disposed at a measurement position, a light interference signal is A/D converted at a regular time interval, and data numbers at timing giving peak and bottom are calculated according to a least-squares method. Based on this, an approximate equation is calculated according to polynomial approximation and a sequence including the number of exponentiation of 2 and converting the data number at a regular frequency interval is calculated. Then, by disposing a measured target at the measurement position, calculating the necessary number of pieces of data for FFT from measured data at each timing according to straight-line approximation and Fourier transforming a light beat signal obtained by an optical interferometer at regular frequency interval, a tomogram having high resolution and high sensitivity can be acquired.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: November 16, 2010
    Assignee: Santec Corporation
    Inventors: Atsushi Morosawa, Changho Chong
  • Patent number: 7800396
    Abstract: A semiconductor integrated circuit includes a circuit block connected to an arithmetic processing unit via a bus, a power supply noise data generator which is configured to generate a power supply noise data signal by converting power supply noise generated in power supply voltage of power supply operates the circuit block, an error detector which is configured to detect an error of data outputted from the circuit block to the bus, and a write controller which is configured to associate power supply noise information based on the power supply noise data signal with data on the bus and write the data in a storage unit, and to stop to write the data in response to the detection of the error by the error detector.
    Type: Grant
    Filed: May 30, 2009
    Date of Patent: September 21, 2010
    Assignee: Fujitsu Limited
    Inventors: Takashi Yamamoto, Takaharu Ishizuka, Toshikazu Ueki, Takeshi Owaki, Atsushi Morosawa
  • Publication number: 20100191942
    Abstract: A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in an FWH instructs the northbridge to inhibit an external instruction. In addition, the firmware save the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU save on the memory to the all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.
    Type: Application
    Filed: March 24, 2010
    Publication date: July 29, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Owaki, Takaharu Ishizuka, Toshikazu Ueki, Makoto Hataida, Yuka Hosokawa, Atsushi Morosawa, Takashi Yamamoto, Daisuke Itou
  • Publication number: 20100077262
    Abstract: An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.
    Type: Application
    Filed: September 4, 2009
    Publication date: March 25, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Atsushi MOROSAWA, Takaharu ISHIZUKA, Toshikazu UEKI, Makoto HATAIDA, Yuka HOSOKAWA, Takeshi OWAKI, Takashi YAMAMOTO, Daisuke ITOU