Abstract: The present disclosure provides a substrate support. The substrate support comprises: a base; a first dielectric portion, disposed on the base, having a substrate support portion on which a substrate is mounted; and a second dielectric portion, disposed around the first dielectric portion, having an edge ring support portion on which an edge ring is mounted, wherein at least one of the first dielectric portion and the second dielectric portion includes a sprayed layer formed of an insulating material.

Abstract: The present invention provides a level shift circuit that can reliably cut off the path of a through current regardless of the state of supply of power to plural circuit sections that operate by different power supplies. The level shift circuit is provided with an input circuit section that operates by a power supply voltage VDD1 and an output circuit section that operates by a power supply voltage VDD2. An inverter circuit, which operates by the power supply voltage VDD1 and converts a control signal that is inputted from the output circuit section, is disposed in the input circuit section. The output of the inverter circuit is used as the output of another inverter circuit that operates by the power supply voltage VDD2 of the output circuit section and as the control signal of the input circuit section.

Abstract: The present invention provides a level shift circuit that can reliably cut off the path of a through current regardless of the state of supply of power to plural circuit sections that operate by different power supplies. The level shift circuit is provided with an input circuit section that operates by a power supply voltage VDD1 and an output circuit section that operates by a power supply voltage VDD2. An inverter circuit, which operates by the power supply voltage VDD1 and converts a control signal that is inputted from the output circuit section, is disposed in the input circuit section. The output of the inverter circuit is used as the output of another inverter circuit that operates by the power supply voltage VDD2 of the output circuit section and as the control signal of the input circuit section.

Abstract: The present invention provides a semiconductor integrated circuit that enhances resistance to an electrostatic discharge (ESD) as needed without re-fabricating masks. In the semiconductor integrated circuit, protection cells are formed within a core circuit. According to the degree of necessity of the ESD resistance, a wiring for connecting each of the protection cells and an output terminal of an ESD trigger detection circuit is formed in a wiring layer.

Abstract: An NMOS diode-connected in a backward direction between a power supply terminal and a ground terminal is provided as a protective element. Further, a band-pass blocking filter for blocking the passage of a frequency component of an ESD current is provided between the power supply terminal and an internal circuit. Thus, the inflow of an ESD current having a high frequency component into the internal circuit is blocked by the filter. When a potential VDD at the power supply terminal rises, the NMOS used as the protective element breaks down precedently. Thus, the voltage at the power supply terminal is reduced and hence the internal circuit is protected from the ESD current.

Abstract: A semiconductor device includes first and second lines, a first transistor configured to electrically connect with the second line, and a second transistor configured to electrically connect the first line and the first transistor, the second transistor being turned ON when a bias voltage for operation is impressed between the first and second lines.

Abstract: An improved electrostatic discharge (ESD) protection structure that is suitable for use in a large-scale CMOS circuit fabrication technology is disclosed. When surge energy enters the first conductor during an ESD event, the surge current is conducted through the first contacts of the first MOS transistors, the second contacts of the first MOS transistors, the fourth conductor, and the third contacts of the second transistors. As each third contact is paired with each second contact, the surge current is conducted from a second contact to the paired third contact. Then, the surge current is conducted through the third contacts, fourth contacts, and the second conductor. In this operation, electric fields are generated in the direction of the first contacts, the second contacts, the fourth conductor, the third contacts, and the fourth contacts.

Abstract: An input buffer circuit includes front stage circuits and a succeeding stage circuit. Each of the front stage circuits has a logic threshold voltage different from each other. The succeeding stage circuit has a P type MOS transistor and an N type MOS transistor connected in series. The succeeding circuit includes inputs connected to the front stage circuit. A logic threshold voltage of the succeeding stage circuit is set to be between the respective logic threshold voltages of the front stage circuits.

Abstract: An input buffer circuit includes front stage circuits and a succeeding stage circuit. Each of the front stage circuits has a logic threshold voltage different from each other. The succeeding stage circuit has a P type MOS transistor and an N type MOS transistor connected in series. The succeeding circuit includes inputs connected to the front stage circuit. A logic threshold voltage of the succeeding stage circuit is set to be between the respective logic threshold voltages of the front stage circuits.