Abstract: A disclosed managing apparatus and image forming apparatus management system ensure confidentiality of information in an image forming apparatus while usability is maintained. An image forming apparatus acquires IC card identifying information with an IC card reader. A management server acquires a user ID associated with the acquired IC card identifying information and use limit information concerning use of the image forming apparatus. A process is performed in the image forming apparatus in accordance with the use limit information.

Abstract: A motor-driven compressor includes a compression mechanism, an electric motor, an inverter, a housing, and a cover defining an accommodation chamber with the housing to accommodate the inverter. The cover includes a plate-shaped body wall and insertion holes extending through a periphery of the body wall. The body wall includes a first surface opposed to the inverter in the accommodation chamber, a second surface, a first thickness portion having a first thickness, and a second thickness portion located around at least one of the insertion holes. The second thickness portion has a second thickness that is smaller than the first thickness and is obtained by recessing the body wall from the first surface toward the second surface.

Abstract: A motor-driven compressor includes a compression mechanism, an electric motor, an inverter, a housing, and a cover defining an accommodation chamber with the housing to accommodate the inverter. The cover includes a plate-shaped body wall and insertion holes extending through a periphery of the body wall. The body wall includes a first surface opposed to the inverter in the accommodation chamber, a second surface, a first thickness portion having a first thickness, and a second thickness portion located around at least one of the insertion holes. The second thickness portion has a second thickness that is smaller than the first thickness and is obtained by recessing the body wall from the first surface toward the second surface.

Abstract: The orbiting base plate has a compression side surface and a back pressure chamber side surface. The gas passage has an opening in the compression side surface of the orbiting base plate between portions of the orbiting spiral wall that face each other, and the gas passage has an opening in the back pressure side surface at a position that faces an area on a radially inner side than the outer circumference of the bearing, so as to feed the refrigerant gas in the compression chamber to the back pressure chamber.

Abstract: The orbiting base plate 61 has a compression side surface and a back pressure chamber side surface. The gas passage 64 has an opening 641 in the compression side surface of the orbiting base plate 61 between portions of the orbiting spiral wall 62 that face each other, and the gas passage 64 has an opening 642 in the back pressure side surface at a position that faces an area on a radially inner side than the outer circumference of the bearing 5, so as to feed the refrigerant gas in the compression chamber 15 to the back pressure chamber 16.

Abstract: A semiconductor device includes a substrate, a low dielectric constant layer formed on the substrate, a first protection insulating layer formed on the low dielectric constant layer, and a trench with an interconnect embedded in formed in the first protection insulating layer and the low dielectric constant layer. The sidewall of the trench has a structure that the surface of the first protection insulating layer protrudes from the surface of the low dielectric constant layer, a second protection insulating layer formed by a chemical vapor deposition technique is embedded at the surface of the low dielectric constant layer in an area below the first protection insulating layer, and the sidewall of the trench is constituted by the second protection insulating layer and the first protection insulating layer.

Abstract: A semiconductor device includes a substrate, a low dielectric constant layer formed on the substrate, a first protection insulating layer formed on the low dielectric constant layer, and a trench with an interconnect embedded in formed in the first protection insulating layer and the low dielectric constant layer. The sidewall of the trench has a structure that the surface of the first protection insulating layer protrudes from the surface of the low dielectric constant layer, a second protection insulating layer formed by a chemical vapor deposition technique is embedded at the surface of the low dielectric constant layer in an area below the first protection insulating layer, and the sidewall of the trench is constituted by the second protection insulating layer and the first protection insulating layer.

Abstract: A trench is formed by a process which removes a damage layer formed on a sidewall of a low dielectric constant layer, a process which forms a second protection insulating layer by a chemical vapor deposition (CVD) technique and forms a second concave portion by covering a sidewall of the low dielectric constant layer with the second protection insulating layer, and a process which shapes the second protection insulating layer by etch back so that a trench has a sidewall that the second protection insulating layer is selectively formed on a surface of the low dielectric constant layer.

Abstract: A trench is formed by a process which removes a damage layer formed on a sidewall of a low dielectric constant layer, a process which forms a second protection insulating layer by a chemical vapor deposition (CVD) technique and forms a second concave portion by covering a sidewall of the low dielectric constant layer with the second protection insulating layer, and a process which shapes the second protection insulating layer by etch back so that a trench has a sidewall that the second protection insulating layer is selectively formed on a surface of the low dielectric constant layer.

Abstract: A method and an apparatus for detecting a partial discharge in a high-voltage transmission and distribution system include detectors which are respectively attached to a power cable and an antenna, such that a first signal and a second signal at a predetermined frequency are extracted using resonators. The first signal is supplied to a differential amplifier via a delay circuit. The second signal is supplied to the differential amplifier via a regulator that includes a variable delay circuit and a variable amplifier. The output from the differential amplifier is demodulated in a demodulator. The signal from the demodulator is supplied to an MPU via an A/D converter to determine the amount of adjustment in phase and amplitude which is to be supplied to the regulator. Then, control is provided such that the output from the differential amplifier is minimized in the absence of partial discharges.

Abstract: Provided is a method of etching a silicon nitride film, which comprises subjecting the silicon nitride film located on copper to dry etching using a mixture of fluorocarbon gas and an inert gas as the reaction gas, the fluorocarbon gas containing CF4 and CHF3 supplied at flow rates in a ratio of 3:7 to 0:1 or contains CF4 and CH2F2 supplied at flow rates in a ratio of 2.5:1 to 0:1, thereby suppressing the formation of copper fluoride.

Abstract: The present invention relates to a method of manufacturing a semiconductor integrated circuit in which a via hole reaching a metal wiring and a concave groove are simultaneously formed in an interlayer film. When the interlayer film and the material of an organic film embedded in the via hole are etched, the etching rate for the material of the organic film with an etching gas is set to be higher than the etching rate for the interlayer film with an etching gas. Thus, plasma etching does not proceed in a state in which the material of the organic film projects from the bottom of the concave groove formed in the interlayer film, and the production of depositions is prevented.

Abstract: Provided is a method of etching a silicon nitride film, which comprises subjecting the silicon nitride film located on copper to dry etching using a mixture of fluorocarbon gas and an inert gas as the reaction gas, the fluorocarbon gas containing CF4 and CHF3 supplied at flow rates in a ratio of 3:7 to 0:1 or contains CF4 and CH2F2 supplied at flow rates in a ratio of 2.5:1 to 0:1, thereby suppressing the formation of copper fluoride.

Abstract: A film containing low dielectric constant MSQ is used for an interlayer insulation film, an opening is provided in the MSQ by use of a resist as a mask, and resist is ashed while the MSQ is exposed. Ashing conditions in this case are set to a low temperature (−20° C. to 60° C.) and lower pressure (5 to 200 mTorr), and RF supply is carried out in the order of bias power and source power. Thus, a CH3 group which determines a low dielectric constant characteristic of the MSQ can be left in the film.

Abstract: A dry etching method, with a gas containing nitrogen added to an etching gas containing a halogen compound for an SiC film, applies a low dielectric constant film to an interlayer insulating film and reduces parasitic capacitance between groove wirings. In manufacturing of a multilayer wiring structure, an SiC layer and an interlayer insulating film are laminated on a lower layer wiring, and a via hole that reaches the surface of the SiC layer and a wiring groove is formed by dry-etching a region of the interlayer insulating film. The exposed SiC layer is then removed by dry etching, using the interlayer insulating film as an etching mask, and the via hole penetrates the SiC layer to the surface of the lower layer wiring. The penetrating via hole and the wiring groove are filled with a conductive material to form a groove wiring connecting with the lower layer wiring.

Abstract: Provided is a method of etching a silicon nitride film, which comprises subjecting the silicon nitride film located on copper to dry etching using a mixture of fluorocarbon gas and an inert gas as the reaction gas, the fluorocarbon gas containing CF4 and CHF3 supplied at flow rates in a ratio of 3:7 to 0:1 or contains CF4 and CH2F2 supplied at flow rates in a ratio of 2.5:1 to 0:1, thereby suppressing the formation of copper fluoride.

Abstract: A semiconductor device manufacturing method according to the invention includes a process for forming an insulating film made of organic material the dielectric constant of which is low and which has a relative dielectric constant lower than that of silicon oxide on a semiconductor substrate, a process for forming a resist film having an opening on the insulating film, a process for dry-etching the insulating film using the resist film as a mask and a process for removing at least a part of the resist film by ashing using the plasma of mixed gas including nitrogen and hydrogen.

Abstract: A dry etching method, with a gas containing nitrogen added to an etching gas containing a halogen compound for an SiC film, applies a low dielectric constant film to an interlayer insulating film and reduces parasitic capacitance between groove wirings. In manufacturing of a multilayer wiring structure, an SiC layer and an interlayer insulating film are laminated on a lower layer wiring, and a via hole that reaches the surface of the SiC layer and a wiring groove is formed by dry-etching a region of the interlayer insulating film. The exposed SiC layer is then removed by dry etching, using the interlayer insulating film as an etching mask, and the via hole penetrates the SiC layer to the surface of the lower layer wiring. The penetrating via hole and the wiring groove are filled with a conductive material to form a groove wiring connecting with the lower layer wiring.

Abstract: A Cu wiring is formed on a higher layer than a Si substrate, and a via plug formed in a via hole communicates with the higher layer and the Si substrate. Etch rates of a HSQ layer surrounding a damascene and the first SiO2 layer formed on the Si substrate change in different modes depending on the ratio of the flow rate of the first reactive gas to that of the second reactive gas. According to the aforementioned structure, a dual damascene structure of the semiconductor device in which there is no necessity for forming a stopper layer formed of silicon nitride between the insulating layers, and a capacitance between wirings can be reduced.

Abstract: The present invention relates to a method of manufacturing a semiconductor integrated circuit in which a via hole reaching a metal wiring and a concave groove are simultaneously formed in an interlayer film. When the interlayer film and the material of an organic film embedded in the via hole are etched, the etching rate for the material of the organic film with an etching gas is set to be higher than the etching rate for the interlayer film with an etching gas. Thus, plasma etching does not proceed in a state in which the material of the organic film projects from the bottom of the concave groove formed in the interlayer film, and the production of depositions is prevented.