Abstract: A semiconductor device includes a memory cell on a semiconductor substrate. The memory cell includes a memory element, a first assistance element, and a second assistance element. The memory element includes a source region and a drain region, and a selection gate and a floating gate in series therebetween. The first assistance element includes a first impurity region and a first gate. The second assistance element includes a second impurity region and a second gate. The first and second gates are electrically connected to the floating gate. The second impurity region is connected to a signal line that is connected to the drain region or a signal line that is connected to the selection gate.

Abstract: A semiconductor memory device includes: a first conductive layer; a second conductive layer; a first insulating film; a first plug; a second plug; a second insulating film having a first opening and a second opening; a first metal film; a second metal film; a first capacitor insulating film formed on the first metal film; a second capacitor insulating film formed on the second metal film; and a third metal film. The second metal film is formed so that an end thereof located away from the first opening extends onto the top surface of the second insulating film. The second metal film is connected at its extending portion to the third metal film.

Abstract: A semiconductor memory device includes: a first conductive layer; a second conductive layer; a first insulating film; a first plug; a second plug; a second insulating film having a first opening and a second opening; a first metal film; a second metal film; a first capacitor insulating film formed on the first metal film; a second capacitor insulating film formed on the second metal film; and a third metal film. The second metal film is formed so that an end thereof located away from the first opening extends onto the top surface of the second insulating film. The second metal film is connected at its extending portion to the third metal film.

Abstract: A reliability test method for a ferroelectric memory device having a ferroelectric capacitor evaluates, under acceleration conditions (acceleration temperature T2 and test time t2), whether or not life of retention characteristics of the ferroelectric memory device is guaranteed under actual use conditions (guarantee temperature T1 and guarantee time t1). The method includes the step of determining test time t2 that is required to evaluate whether the life of the retention characteristics is guaranteed or not, based on temperature dependence of change with time of a bit line voltage that is generated when data written to the ferroelectric memory device is read.

Abstract: After a capacitor device including a lower electrode, a capacitor dielectric film made from a ferroelectric film and an upper electrode is formed on a substrate, an insulating film covering the capacitor device is formed. Subsequently, the capacitor device covered with the insulating film is annealed for crystallizing the ferroelectric film.

Abstract: An accelerated test method evaluates, under accelerated conditions (a temperature T2 and a voltage V2), an endurance characteristic of a ferroelectric memory device having a capacitor element including a ferroelectric film under actual operating conditions (a temperature T1 and a voltage V1). An acceleration factor (K) required to evaluate the endurance characteristic is derived by using an expression: logK=A(1/V1?1/V2)+B(1/V1T1?1/V2T2) (where each of A and B is a constant).

Abstract: A reliability test method for a ferroelectric memory device having a ferroelectric capacitor evaluates, under acceleration conditions (acceleration temperature T2 and test time t2), whether or not life of retention characteristics of the ferroelectric memory device is guaranteed under actual use conditions (guarantee temperature T1 and guarantee time t1). The method includes the step of determining test time t2 that is required to evaluate whether the life of the retention characteristics is guaranteed or not, based on temperature dependence of change with time of a bit line voltage that is generated when data written to the ferroelectric memory device is read.

Abstract: An etchant for etching at least one of a titanium material and silicon oxide includes a mixed liquid of HCl, NH4Fand H2O. When the etchant has a NH4F/HCl molar ratio of less than one, only the titanium material is etched. When the etchant has a NH4F/HCl molar ratio of more than one, only silicon oxide is etched. When the etchant has a NH4F/HCl molar ratio of one, the titanium material and silicon oxide are etched at the same rate.

Abstract: An accelerated test method evaluates, under accelerated conditions (a temperature T2 and a voltage V2), an endurance characteristic of a ferroelectric memory device having a capacitor element including a ferroelectric film under actual operating conditions (a temperature T1 and a voltage V1). An acceleration factor (K) required to evaluate the endurance characteristic is derived by using an expression: logK=A(1/V1−1/V2)+B(1/V1T1−1/V2T2) (where each of A and B is a constant).

Abstract: After a capacitor device including a lower electrode, a capacitor dielectric film made from a ferroelectric film and an upper electrode is formed on a substrate, an insulating film covering the capacitor device is formed. Subsequently, the capacitor device covered with the insulating film is annealed for crystallizing the ferroelectric film.

Abstract: An etchant for etching at least one of a titanium material and silicon oxide includes a mixed liquid of HCl, NH4F and H2O. When the etchant has a NH4F/HCl molar ratio of less than one, only the titanium material is etched. When the etchant has a NH4F/HCl molar ratio of more than one, only silicon oxide is etched. When the etchant has a NH4F/HCl molar ratio of one, the titanium material and silicon oxide are etched at the same rate.

Abstract: An etchant for etching at least one of a titanium material and silicon oxide includes a mixed liquid of HCl, NH4Fand H2O. When the etchant has a NH4F/HCl molar ratio of less than one, only the titanium material is etched. When the etchant has a NH4F/HCl molar ratio of more than one, only silicon oxide is etched. When the etchant has a NH4F/HCl molar ratio of one, the titanium material and silicon oxide are etched at the same rate.

Abstract: An underlying conductive film made of iridium and having a thickness of about 0.1 &mgr;m is formed in a contact hole formed in an insulating film covering a transistor formed in a substrate, except in the top portion of the contact hole. The underlying conductive film covers the sidewall portions of the contact hole and the top surface of the drain region but does not completely fill in the contact hole. A plug made of platinum is filled in the contact hole up to the top portion thereof. Over the contact hole of the insulating film, there is formed a capacitor composed of a lower electrode made of platinum, a capacitor insulating film made of SrBi2Ta2O9, and an upper electrode made of platinum in contact relation with the respective upper ends of the underlying conductive film and the plug.

Abstract: A via hole having a bottom is formed in a substrate and then a conductor layer is formed at least over a sidewall of the via hole. Thereafter, the substrate is thinned by removing a portion of the substrate opposite to another portion of the substrate in which the via hole is formed such that the conductor layer is exposed.

Abstract: An etchant for etching at least one of a titanium material and silicon oxide includes a mixed liquid of HCl, NH4F and H2O. When the etchant has a NH4F/HCl molar ratio of less than one, only the titanium material is etched. When the etchant has a NH4F/HCl molar ratio of more than one, only silicon oxide is etched. When the etchant has a NH4F/HCl molar ratio of one, the titanium material and silicon oxide are etched at the same rate.

Abstract: An underlying conductive film made of iridium and having a thickness of about 0.1 &mgr;m is formed in a contact hole formed in an insulating film covering a transistor formed in a substrate, except in the top portion of the contact hole. The underlying conductive film covers the sidewall portions of the contact hole and the top surface of the drain region but does not completely fill in the contact hole. A plug made of platinum is filled in the contact hole up to the top portion thereof. Over the contact hole of the insulating film, there is formed a capacitor composed of a lower electrode made of platinum, a capacitor insulating film made of SrBi2Ta2O9, and an upper electrode made of platinum in contact relation with the respective upper ends of the underlying conductive film and the plug.

Abstract: A ferroelectric capacitor comprising a lower electrode, a ceramic capacity film made of a ferroelectric substance and an upper electrode is provided on a substrate insulating film formed on a semiconductor substrate. A layer insulating film is formed on the semiconductor substrate so as to cover the ferroelectric capacitor. An electrode wiring is formed on the layer insulating film. A length L of the surface of the ceramic capacity film which is present between an intersection of the side of the upper electrode and the upper face of the ceramic capacity film and an intersection of the side of the ceramic capacity film and the upper face of the lower electrode and a thickness D of the ceramic capacity film have a relationship of L.gtoreq.2D.