Patents by Inventor Atsushi Ogino

Atsushi Ogino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190181215
    Abstract: Device structures and fabrication methods for an on-chip resistor. A resistor body is formed on an interlayer dielectric layer of a contact level. A contact is formed that extends vertically through the interlayer dielectric layer. One or more dielectric layers are formed over the contact level, and a metal feature is formed in the one or more dielectric layers. The metal feature is at least in part in direct contact with a portion of the resistor body.
    Type: Application
    Filed: December 7, 2017
    Publication date: June 13, 2019
    Inventors: Atsushi Ogino, Lin Hu, Brian Greene
  • Patent number: 10229918
    Abstract: Devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a dielectric layer, a first, a second, and a third hardmask layer, and a lithography stack; patterning a first set of lines; patterning a second set of lines between the first set of lines; etching to define a combination of the first and second set of lines; depositing a second lithography stack; patterning a third set of lines in a direction perpendicular to the first and second set of lines; etching to define the third set of lines, leaving an OPL; depositing a spacer over the OPL; etching the spacer, leaving a vertical set of spacers; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: March 12, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Atsushi Ogino
  • Patent number: 10147783
    Abstract: Structures for an on-chip capacitor and methods of forming an on-chip capacitor. A metal terminal is formed that has a side edge. Metal fingers are formed that have a parallel arrangement. Floating islands comprised of a metal are formed and are electrically isolated from the metal fingers. Each of the metal fingers has an end and extends from the side edge of the metal terminal toward the end. Each of the floating islands is arranged in a spaced relationship with the end of a respective one of the metal fingers.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: December 4, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Atsushi Ogino, Vikrant Chauhan, Kong Boon Yeap, Ahmed Hassan
  • Publication number: 20180269275
    Abstract: Structures for an on-chip capacitor and methods of forming an on-chip capacitor. A metal terminal is formed that has a side edge. Metal fingers are formed that have a parallel arrangement. Floating islands comprised of a metal are formed and are electrically isolated from the metal fingers. Each of the metal fingers has an end and extends from the side edge of the metal terminal toward the end. Each of the floating islands is arranged in a spaced relationship with the end of a respective one of the metal fingers.
    Type: Application
    Filed: March 20, 2017
    Publication date: September 20, 2018
    Inventors: Atsushi Ogino, Vikrant Chauhan, Kong Boon Yeap, Ahmed Hassan
  • Publication number: 20180261538
    Abstract: Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer. A viabar electrically connects the first metal layer to the third metal layer, the viabar running in the first direction wherein the viabar vertically extends from the first metal layer to the third metal layer. A method of manufacturing the IC is provided.
    Type: Application
    Filed: May 10, 2018
    Publication date: September 13, 2018
    Inventors: Erdem Kaltalioglu, Atsushi Ogino
  • Patent number: 9997456
    Abstract: Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer. A viabar electrically connects the first metal layer to the third metal layer, the viabar running in the first direction wherein the viabar vertically extends from the first metal layer to the third metal layer. A method of manufacturing the IC is provided.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: June 12, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Erdem Kaltalioglu, Atsushi Ogino
  • Patent number: 9991202
    Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: June 5, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jim S. Liang, Justin C. Long, Atsushi Ogino
  • Publication number: 20180138187
    Abstract: Devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a dielectric layer, a first, a second, and a third hardmask layer, and a lithography stack; patterning a first set of lines; patterning a second set of lines between the first set of lines; etching to define a combination of the first and second set of lines; depositing a second lithography stack; patterning a third set of lines in a direction perpendicular to the first and second set of lines; etching to define the third set of lines, leaving an OPL; depositing a spacer over the OPL; etching the spacer, leaving a vertical set of spacers; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks.
    Type: Application
    Filed: July 28, 2017
    Publication date: May 17, 2018
    Applicant: GLOBALFOUNDRIES Inc.
    Inventor: Atsushi OGINO
  • Publication number: 20180096933
    Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.
    Type: Application
    Filed: November 22, 2017
    Publication date: April 5, 2018
    Inventors: Jim Shih-Chun Liang, Atsushi Ogino, Justin C. Long
  • Patent number: 9899324
    Abstract: A method includes providing a semiconductor substrate having horizontal and vertical scribe lines thereon defining semiconductor areas for printed circuits and/or semiconductor devices, and forming a metallic structure on the semiconductor substrate to serve as a bus bar for the printed circuits and/or semiconductor devices. A semiconductor structure is realized with the method, the semiconductor structure including a semiconductor substrate having horizontal and vertical scribe lines thereon defining semiconductor areas for printed circuits and/or semiconductor devices, a metallic structure on the semiconductor substrate serving as a bus bar for the printed circuits and/or semiconductor devices, and printed circuits and/or semiconductor devices in the semiconductor areas.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: February 20, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shafaat Ahmed, Sadanand Vinayak Despande, Atsushi Ogino
  • Publication number: 20180033718
    Abstract: Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer. A viabar electrically connects the first metal layer to the third metal layer, the viabar running in the first direction wherein the viabar vertically extends from the first metal layer to the third metal layer. A method of manufacturing the IC is provided.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 1, 2018
    Inventors: Erdem Kaltalioglu, Atsushi Ogino
  • Patent number: 9865473
    Abstract: Devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a dielectric layer, a first hardmask layer, a second hardmask layer, a third hardmask layer, and a lithography stack; patterning a first set of lines; patterning a second set of lines between the first set of lines; etching to define a combination of the first and second set of lines; depositing a second lithography stack; patterning a set of islands; etching to define the set of islands, leaving an OPL; depositing a spacer over the OPL; etching the spacer, leaving a vertical set of spacers; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Atsushi Ogino
  • Patent number: 9793216
    Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Joyeeta Nag, Jim Shih-Chun Liang, Domingo A. Ferrer Luppi, Atsushi Ogino, Andrew H. Simon, Michael P. Chudzik
  • Patent number: 9748251
    Abstract: Devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a dielectric layer, a first hardmask layer, a second hardmask layer, a third hardmask layer, and a lithography stack; patterning a first set of lines; patterning a second set of lines between the first set of lines; etching to define a combination of the first and second set of lines; depositing a second lithography stack; patterning a third set of lines in a direction perpendicular to the first and second set of lines; etching to define the third set of lines, leaving an OPL; depositing a spacer over the OPL; etching the spacer, leaving a vertical set of spacers; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: August 29, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Atsushi Ogino
  • Publication number: 20170213792
    Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.
    Type: Application
    Filed: January 26, 2016
    Publication date: July 27, 2017
    Inventors: Joyeeta Nag, Jim Shih-Chun Liang, Domingo A. Ferrer Luppi, Atsushi Ogino, Andrew H. Simon, Michael P. Chudzik
  • Patent number: 9589912
    Abstract: A first aspect of the disclosure provides for an integrated circuit structure. The integrated circuit structure may comprise a first metal structure in a first dielectric layer on a substrate in a crack stop area; and a first crack stop structure in a second dielectric layer, the first crack stop structure being over the first metal structure and including: a first metal fill contacting the first metal structure; and an air seam substantially separating the first metal fill and the second dielectric layer.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: March 7, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jim S. Liang, Atsushi Ogino, Stephen E. Greco, Roger A. Quon
  • Patent number: 9589911
    Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure with a metal crack stop and methods of forming the same. An IC structure according to embodiments of the present disclosure can include an insulator positioned over a substrate; a barrier film positioned over the insulator; an interlayer dielectric positioned over the barrier film; and a metal crack stop positioned over the substrate and laterally adjacent to each of the insulator, the barrier film, and the interlayer dielectric, wherein the metal crack stop includes a sidewall having a first recess therein, and wherein a horizontal interface between the barrier film and the interlayer dielectric intersects the sidewall of the metal crack stop.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: March 7, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jim S. Liang, Atsushi Ogino, Roger A. Quon, Stephen E. Greco
  • Publication number: 20170062355
    Abstract: A first aspect of the disclosure provides for an integrated circuit structure. The integrated circuit structure may comprise a first metal structure in a first dielectric layer on a substrate in a crack stop area; and a first crack stop structure in a second dielectric layer, the first crack stop structure being over the first metal structure and including: a first metal fill contacting the first metal structure; and an air seam substantially separating the first metal fill and the second dielectric layer.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 2, 2017
    Inventors: Jim S. Liang, Atsushi Ogino, Stephen E. Greco, Roger A. Quon
  • Publication number: 20170062354
    Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure with a metal crack stop and methods of forming the same. An IC structure according to embodiments of the present disclosure can include an insulator positioned over a substrate; a barrier film positioned over the insulator; an interlayer dielectric positioned over the barrier film; and a metal crack stop positioned over the substrate and laterally adjacent to each of the insulator, the barrier film, and the interlayer dielectric, wherein the metal crack stop includes a sidewall having a first recess therein, and wherein a horizontal interface between the barrier film and the interlayer dielectric intersects the sidewall of the metal crack stop.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 2, 2017
    Inventors: Jim S. Liang, Atsushi Ogino, Roger A. Quon, Stephen E. Greco
  • Publication number: 20170005037
    Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 5, 2017
    Inventors: Jim S. Liang, Justin C. Long, Atsushi Ogino