Patents by Inventor Atsushi Onogi

Atsushi Onogi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10141411
    Abstract: A semiconductor device includes a semiconductor substrate of silicon carbide, and a temperature sensor portion. The semiconductor substrate includes a portion in which an n-type drift region and a p-type body region are laminated. The temperature sensor portion is disposed in the semiconductor substrate and is separated from the drift region by the body region. The temperature sensor portion includes an n-type cathode region being in contact with the body region, and a p-type anode region separated from the body region by the cathode region.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: November 27, 2018
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Atsushi Onogi, Toru Onishi, Shuhei Mitani, Yusuke Yamashita, Katsuhiro Kutsuki
  • Patent number: 9941366
    Abstract: Described herein is a semiconductor device comprising: a semiconductor substrate; a trench provided at a surface of the semiconductor substrate; a first insulating layer covering an inner surface of the trench; and a second insulating layer located at a surface of the first insulating layer in the trench. A refraction index of the first insulating layer is larger than a refraction index of the second insulating layer.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: April 10, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Atsushi Onogi, Shinichiro Miyahara
  • Patent number: 9871098
    Abstract: A semiconductor device may include a semiconductor substrate in which a semiconductor element is provided, and an insulation film provided on the semiconductor substrate, in which the semiconductor substrate may include a first portion and a second portion which has a thickness thinner than a thickness of the first portion, an upper surface of the second portion may be positioned lower than an upper surface of the first portion, a recess extending in a thickness direction of the semiconductor substrate may be provided on the upper surface of the second portion located at a position where the first portion and the second portion adjoin to each other, and the insulation film may extend over from the first portion to the second portion, and fill the recess.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: January 16, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Jun Saito, Atsushi Onogi, Sachiko Aoi, Shoji Mizuno
  • Publication number: 20170309716
    Abstract: A semiconductor device includes a semiconductor substrate in which a semiconductor element is provided and a covering insulation film provided on the semiconductor substrate. The semiconductor substrate includes a first portion and a second portion which has a thickness thinner than a thickness of the first portion. A step portion is provided at a part where the first portion and the second portion adjoin to each other. A corner member is provided at a corner between a side surface of the step portion and an upper surface of the second portion. An upper surface of the corner member slopes downward from the side surface of the step portion toward the second portion. The covering insulation film extends over from the first portion to the second portion, and covers the corner member.
    Type: Application
    Filed: July 22, 2015
    Publication date: October 26, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Jun SAITO, Atsushi ONOGI, Sachiko AOI, Shinichiro MIYAHARA
  • Publication number: 20170288014
    Abstract: A semiconductor device may include a semiconductor substrate in which a semiconductor element is provided, and an insulation film provided on the semiconductor substrate, in which the semiconductor substrate may include a first portion and a second portion which has a thickness thinner than a thickness of the first portion, an upper surface of the second portion may be positioned lower than an upper surface of the first portion, a recess extending in a thickness direction of the semiconductor substrate may be provided on the upper surface of the second portion located at a position where the first portion and the second portion adjoin to each other, and the insulation film may extend over from the first portion to the second portion, and fill the recess.
    Type: Application
    Filed: July 22, 2015
    Publication date: October 5, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Jun SAITO, Atsushi ONOGI, Sachiko AOI, Shoji MIZUNO
  • Publication number: 20170271457
    Abstract: A semiconductor device includes a semiconductor substrate of silicon carbide, and a temperature sensor portion. The semiconductor substrate includes a portion in which an n-type drift region and a p-type body region are laminated. The temperature sensor portion is disposed in the semiconductor substrate and is separated from the drift region by the body region. The temperature sensor portion includes an n-type cathode region being in contact with the body region, and a p-type anode region separated from the body region by the cathode region.
    Type: Application
    Filed: February 17, 2017
    Publication date: September 21, 2017
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Atsushi ONOGI, Toru ONISHI, Shuhei MITANI, Yusuke YAMASHITA, Katsuhiro KUTSUKI
  • Patent number: 9679989
    Abstract: A method of manufacturing an insulated gate type switching device includes forming a gate trench that has a first portion with a first width in a first direction and a second portion with a second width in the first direction, the second width being wider than the first width. In an oblique implantation, second conductivity type impurities are irradiated at an irradiation angle inclined around an axis orthogonal to the first direction. The first width, the second width, and the irradiation angle are set such that the second conductivity type impurities are suppressed, at a first side surface of the first portion, from being implanted into a part below a lower end of a second semiconductor region, and at a second side surface of the second portion, the impurities are implanted into the part below the lower end of the second semiconductor region.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: June 13, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Toru Onishi, Atsushi Onogi, Tadashi Misumi, Yusuke Yamashita, Yuichi Takeuchi
  • Publication number: 20170092742
    Abstract: A method of manufacturing an insulated gate type switching device includes forming a gate trench that has a first portion with a first width in a first direction and a second portion with a second width in the first direction, the second width being wider than the first width. In an oblique implantation, second conductivity type impurities are irradiated at an irradiation angle inclined around an axis orthogonal to the first direction. The first width, the second width, and the irradiation angle are set such that the second conductivity type impurities are suppressed, at a first side surface of the first portion, from being. implanted into a part below a lower end of a second semiconductor region, and at a second side surface of the second portion, the impurities are implanted into the part below the lower end of the second semiconductor region.
    Type: Application
    Filed: August 12, 2016
    Publication date: March 30, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Toru ONISHI, Atsushi ONOGI, Tadashi MISUMI, Yusuke YAMASHITA, Yuichi TAKEUCHI
  • Publication number: 20160315157
    Abstract: Described herein is a semiconductor device comprising: a semiconductor substrate; a trench provided at a surface of the semiconductor substrate; a first insulating layer covering an inner surface of the trench; and a second insulating layer located at a surface of the first insulating layer in the trench. A refraction index of the first insulating layer is larger than a refraction index of the second insulating layer.
    Type: Application
    Filed: October 14, 2014
    Publication date: October 27, 2016
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Atsushi ONOGI, Shinichiro MIYAHARA
  • Publication number: 20160133741
    Abstract: A silicon carbide semiconductor device includes a MOSFET and a peripheral high-breakdown-voltage structure. A source region has a first recess. Trenches extend from the bottom of the first recess. A gate insulating film has an extension the shape of which follows the shape of the first recess. The surface of a gate electrode is positioned to be flush with or below the upper surface of the extension.
    Type: Application
    Filed: November 2, 2015
    Publication date: May 12, 2016
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hideo MATSUKI, Jun SAKAKIBARA, Sachiko AOI, Yukihiko WATANABE, Atsushi ONOGI
  • Patent number: 9178033
    Abstract: A manufacturing method of a semiconductor device includes: a semiconductor substrate including a drain, a drift making contact with a front face of the drain, a body contacting with a front face of the drift, a source provided in part of a front face of the body, and a floating surrounded by the drift; and a gate including an insulator formed on an inner wall of a trench and a electrode disposed inside the insulator and which has a bottom portion contacting with the floating, the manufacturing method includes: forming the trench in a semiconductor wafer so as to have a bottom portion in which an end portion in a short direction perpendicular to a longitudinal direction thereof is deeper than a central portion; injecting an impurity ions into the bottom portion of the trench; and forming the central portion of the trench in the short direction to be deepened.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: November 3, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Atsushi Onogi
  • Patent number: 9112024
    Abstract: A lateral semiconductor device including a semiconductor substrate; a buried oxide layer formed on the semiconductor substrate, and an active layer formed on the buried oxide layer. The active layer includes a first conductivity type well region, a second conductivity type well region, and a first conductivity type drift region interposed between the first conductivity type well region and the second conductivity type well region. A region where current flows because of carriers moving between the first conductivity type well region and the second conductivity type well region, and a region where no current flows are formed alternately between the first conductivity type well region and the second conductivity type well region, in a direction perpendicular to a carrier moving direction when viewed in a plan view.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: August 18, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Atsushi Onogi, Hiroomi Eguchi, Takashi Okawa
  • Patent number: 9048107
    Abstract: A semiconductor device includes a semiconductor layer; a first type of a first semiconductor element that is arranged in a first element region of the semiconductor layer, has first and second main electrodes, and switches current; and a second type of a second semiconductor element that is arranged in a second element region of the semiconductor layer, has third and fourth main electrodes, and freewheels the current. The first and second element regions are adjacent in a direction orthogonal to a direction in which current flows, and are formed in a loop shape over the entire element region when the semiconductor layer is viewed from above. The first main electrode is electrically connected to the third main electrode, and the second main electrode is electrically connected to the fourth main electrode.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: June 2, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hiroomi Eguchi, Atsushi Onogi, Takashi Okawa, Kiyoharu Hayakawa
  • Patent number: 8871643
    Abstract: A manufacturing method for manufacturing a lateral semiconductor device having an SOI (Silicon on Insulator) substrate, the lateral semiconductor device comprising a semiconductor layer that includes a buried oxide layer and a drift region, the manufacturing method comprising an etching process of etching, by a predetermined depth, a LOCOS oxide that projects from a surface of the semiconductor layer by a predetermined thickness and is embedded in the semiconductor layer by a predetermined thickness, and a trench forming process of simultaneously forming a first trench extending from the drift region toward the buried oxide layer, and a second trench extending from a portion obtained by the etching in the etching process toward the buried oxide layer, at a same etching rate, and stopping forming the first trench and the second trench at a time when the second trench reaches the buried oxide layer.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: October 28, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hiroomi Eguchi, Takashi Okawa, Atsushi Onogi
  • Publication number: 20140295633
    Abstract: A manufacturing method of a semiconductor device includes: a semiconductor substrate including a drain, a drift making contact with a front face of the drain, a body contacting with a front face of the drift, a source provided in part of a front face of the body, and a floating surrounded by the drift; and a gate including an insulator formed on an inner wall of a trench and a electrode disposed inside the insulator and which has a bottom portion contacting with the floating, the manufacturing method includes: forming the trench in a semiconductor wafer so as to have a bottom portion in which an end portion in a short direction perpendicular to a longitudinal direction thereof is deeper than a central portion; injecting an impurity ions into the bottom portion of the trench; and forming the central portion of the trench in the short direction to be deepened.
    Type: Application
    Filed: March 7, 2014
    Publication date: October 2, 2014
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Atsushi ONOGI
  • Publication number: 20140035036
    Abstract: A lateral semiconductor device including a semiconductor substrate; a buried oxide layer formed on the semiconductor substrate, and an active layer formed on the buried oxide layer. The active layer includes a first conductivity type well region, a second conductivity type well region, and a first conductivity type drift region interposed between the first conductivity type well region and the second conductivity type well region. A region where current flows because of carriers moving between the first conductivity type well region and the second conductivity type well region, and a region where no current flows are formed alternately between the first conductivity type well region and the second conductivity type well region, in a direction perpendicular to a carrier moving direction when viewed in a plan view.
    Type: Application
    Filed: May 17, 2011
    Publication date: February 6, 2014
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Atsushi Onogi, Hiroomi Eguchi, Takashi Okawa
  • Publication number: 20130330446
    Abstract: A food packaging container and a packaging method are provided which ensure convenient use of the container when and after an outer bag is opened. An individual wrapping sheet (2) for individually wrapping a chewing gum piece (1) is dividable into a separation portion (2A) and a fixing portion (2B) longitudinally of the chewing gum piece (1). A plurality of individually wrapped chewing gum pieces (1) (food units (3)) are aligned side by side on a rear outer packaging material (51), and a front outer packaging material (52) is folded along one edge (53) of the rear outer packaging material (51) to cover upper surfaces of the food units (3). The rear outer packaging material (51) and the front outer packaging material (52) are combined with each other with their peripheral edge portions sealed with a seal portion (7).
    Type: Application
    Filed: February 7, 2012
    Publication date: December 12, 2013
    Applicant: LOTTE CO., LTD.
    Inventors: Atsushi Onogi, Kaori Horie
  • Publication number: 20130323356
    Abstract: A packaging container is provided, which is configured such that a plurality of food pieces are contained in anteroposteriorly overlapping relation in a plurality of rows, and satisfies requirements for the compactness of the container and the pick-out easiness for picking out each of the food pieces. In a packaging container (A) having a slidable configuration, chewing gum pieces (40) (food strips) can be contained upright in side-by-side relation in a front chamber (L) and in a rear chamber (B) located behind the front chamber (L). The rear chamber (B) is combined with the front chamber (L) so as to be slidable upward with respect to the front chamber (L).
    Type: Application
    Filed: February 15, 2012
    Publication date: December 5, 2013
    Applicant: LOTTE CO., LTD.
    Inventors: Atsushi Onogi, Kaori Horie, Mitsuko Ogaki
  • Publication number: 20130309867
    Abstract: A manufacturing method for manufacturing a lateral semiconductor device having an SOI (Silicon on Insulator) substrate, the lateral semiconductor device comprising a semiconductor layer that includes a buried oxide layer and a drift region, the manufacturing method comprising an etching process of etching, by a predetermined depth, a LOCOS oxide that projects from a surface of the semiconductor layer by a predetermined thickness and is embedded in the semiconductor layer by a predetermined thickness, and a trench forming process of simultaneously forming a first trench extending from the drift region toward the buried oxide layer, and a second trench extending from a portion obtained by the etching in the etching process toward the buried oxide layer, at a same etching rate, and stopping forming the first trench and the second trench at a time when the second trench reaches the buried oxide layer.
    Type: Application
    Filed: February 8, 2011
    Publication date: November 21, 2013
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiroomi Eguchi, Takashi Okawa, Atsushi Onogi
  • Patent number: D842698
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: March 12, 2019
    Assignees: LOTTE CO., LTD., HOSOKAWA YOKO CO., LTD.
    Inventors: Yuichiro Moriyama, Takuro Sakai, Yuki Sugata, Atsushi Onogi, Yuka Shibata, Kazuhiro Umenaka