Abstract: A high speed buffer amplifier circuit comprising a first inverter including a driver transistor, a second inverter which receives the output signal from the first inverter, and, a control transistor which is driven by the output signal from the second inverter and which operates so as to accelerate the effect of the input signal applied between the gate and the source electrode of the driver transistor of the first inverter.

Abstract: A decoder circuit used in a semiconductor memory device including a first and second voltage terminals; a NOR gate circuit including a plurality of inverter transistors for receiving address signals and connected in parallel between the first voltage terminal and a common output node, and a positive feedback transistor for positively feeding back a signal on the common output node and operatively connected between the second voltage terminal and the common output node; and a device, operatively connected between the second voltage terminal and the common output node, for conductively connecting the second voltage terminal to the node for a predetermined period in response to the changing of the address signals.

Abstract: A constant-current source circuit and a differential amplifier using the same. The temperature compensation of the output current of the constant-current source circuit is effected by using the threshold voltage characteristic of a transistor such as a MOS transistor or a bipolar transistor. The constant-current source circuit includes one or more constant-current source circuit units. When the constant-current source circuit includes two constant-current source circuit units, one of the units has a positive temperature coefficient and the other has a negative temperature coefficient. The output currents of these two units are combined by a current synthesizing circuit so as to realize any desired temperature characteristic.

Abstract: A high-speed static-type semiconductor memory device having static-type memory cells each being arranged at an intersection between a word line and a bit line pair. The memory device comprises a circuit means which discharges the electric charges of all the bit lines for a predetermined time period when an input address is switched, so that the potentials of the bit lines become lower than or equal to a low potential level of a bit line signal, thereby enabling the rapid readout of data from a selected memory cell.

Abstract: A sense amplifier circuit used in, for example, a MIS static RAM includes a differential amplifier (Q.sub.11 through Q.sub.14) for sensing and amplifying the difference in potential between two input lines (DB and DB) and generating two bipolar differential signals (D and D) and a pull-down circuit (Q.sub.15) for establishing a reference potential (V.sub.REF) for the differential amplifier. A compensation circuit (Q.sub.16, Q.sub.17 and Q.sub.18) is provided for detecting the in-phase component of the input lines so as to control the pull-down circuit. Therefore, the fluctuation of the reference potential follows the fluctuation of the in-phase component of the input lines so that a stable and high-speed sensing operation is effected.

Abstract: A static type semiconductor memory device including a plurality of cell array blocks which are formed by dividing a memory cell array in a direction of word lines and in a direction of bit lines. Each cell array block includes divided word lines and divided bit lines formed by dividing the word lines and the bit lines, respectively, with the access to a selected memory cell being effected by selecting only a divided word line and a divided bit line of the cell array block containing the selected memory cell.

Abstract: A high density static RAM integrated circuit including a pair of bit lines to which pull-up loads are respectively connected, a plurality of memory cells which are connected across the pair of bit lines, a pair of data buses which are connected to the pair of bit lines, and a sense amplifier which is connected to the pair of bit lines through the pair of data buses, the pair of data buses being respectively provided with charging circuits each of which has a control terminal for varying a pull-up current, amplified outputs of the sense amplifier being fed back to the control terminals of the charging circuits, the data bus on a high potential side being charged by the corresponding charging circuit. As a result, the current which flows across a common data bus line connected to a higher side of the selected bit lines is increased, thereby enabling a high speed read out operation in the high density static RAM.

Abstract: A trigger pulse generator generates trigger pulses synchronized with the rising edges and falling edges of an input signal and is used, for example, in a semiconductor memory device in order to shorten the access time. The trigger pulse generator according to the present invention comprises: an amplifier which outputs a non-inverted signal of the input signal and an inverted signal of the input signal; a pair of depletion-type MIS transistors whose drains or sources are connected to the non-inverting output terminal and to the inverting output terminal of the amplifier and whose gate electrodes are connected to the inverting output terminal and the non-inverting output terminal, respectively; and a gate circuit which is connected to the sources or drains of the pair of depletion-type MIS transistors and which outputs the trigger pulses.

Abstract: A static type semiconductor memory device has a power down mode in which an operating voltage for peripheral circuits, such as decoder circuits, is turned off when the memory chip is in a non-selected condition. The static type semiconductor memory device comprises first transistors, which are connected to a pair of data buses and which pull down the potentials of the pair of data buses to a medium potential when the memory chip has changed from a selected condition, to the non-selected condition and second transistors which are connected to the pair of data buses and which pull up the potentials of the pair of data buses to a high potential when the memory chip has changed from a non-selected condition to a selected condition.

Abstract: A static type semiconductor RAM device having a plurality of memory cells disposed at the cross points between word lines and bit lines, load circuits each connected between one of the bit lines and a voltage source, and, a charging circuit which electrically charges all the bit lines during the short time when all the word lines are in a non-selected condition.