Patents by Inventor Atsushi Saita
Atsushi Saita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8299350Abstract: With the method for manufacturing the solar cell module 100 according to the present embodiment, the width W1 of the connection region C in which the wiring member 11 and the connecting electrode 40 are electrically connected is set to be larger than the substantially half of the width W2 of the wiring member 11 in the thermocompression bonding process of the wiring member 11 using the resin adhesive 12 including the particles 13 onto the principal surface of the solar cell 10.Type: GrantFiled: August 1, 2008Date of Patent: October 30, 2012Assignee: Sanyo Electric Co., Ltd.Inventors: Atsushi Saita, Yukihiro Yoshimine, Shigeyuki Okamoto, Yasufumi Tsunomura, Shigeharu Taira, Hiroshi Kanno, Haruhisa Hashimoto
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Patent number: 8110895Abstract: A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with: a bridge electrically connecting the first via and the second via; and a conductive pattern provided around the bridge, the outer edge of the conductive pattern being located outside the outer edge of the first wiring pattern and the second wiring pattern in the first wiring layer. The bridge functions as a coplanar line and suppresses generation of electromagnetic field.Type: GrantFiled: May 27, 2010Date of Patent: February 7, 2012Assignee: Sanyo Electric Co., Ltd.Inventors: Toshikazu Imaoka, Tetsuro Sawai, Atsushi Saita, Takeshi Yamaguchi
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Publication number: 20110284050Abstract: Provided is a solar cell module (100) in which the interval ?1 from the core (20A) of the first connecting member 20 to the light receiving surface (10A) is substantially the same as the interval ?2 from the core (20A) of the second connecting member (20) to the back surface 10B.Type: ApplicationFiled: December 15, 2009Publication date: November 24, 2011Applicant: SANYO ELECTRIC CO., LTD.Inventors: Atsushi Saita, Yukihiro Yoshimine
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Publication number: 20110017261Abstract: In a solar cell module 100, the wiring member 11 is connected onto the connection electrode 40 through a resin adhesive 12; and the connection electrode 40 includes a plurality of projections 40a which are in direct contact with the wiring member.Type: ApplicationFiled: February 18, 2009Publication date: January 27, 2011Applicant: SANYO ELECTRIC CO., LTD.Inventors: Atsushi Saita, Hiroshi Kanno
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Publication number: 20100315790Abstract: A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with: a bridge electrically connecting the first via and the second via; and a conductive pattern provided around the bridge, the outer edge of the conductive pattern being located outside the outer edge of the first wiring pattern and the second wiring pattern in the first wiring layer. The bridge functions as a coplanar line and suppresses generation of electromagnetic field.Type: ApplicationFiled: May 27, 2010Publication date: December 16, 2010Applicant: Sanyo Electric Co., Ltd.Inventors: Toshikazu Imaoka, Tetsuro Sawai, Atsushi Saita, Takeshi Yamaguchi
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Publication number: 20100282297Abstract: A solar cell comprises a light-receiving side electrode layer 2 a rear side electrode layer 4 and a stacked body 3 placed between the light-receiving side electrode layer 2 and the rear side electrode layer 4, wherein the stacked body 3 includes a first photoelectric conversion section 31, and a reflection layer 32 configured to reflect part of light, which is transmitted through the first photoelectric conversion section 31, to the first photoelectric conversion section 31 side, and the reflection layer 32 includes a MgZnO layer 32b made of MgZnO and a contact layer 32a inserted between the MgZnO layer 32b and the first photoelectric conversion section31.Type: ApplicationFiled: October 30, 2008Publication date: November 11, 2010Applicant: SANYO ELECTRIC CO., LTD.Inventors: Takeyuki Sekimoto, Shigeo Yata, Atsushi Saita
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Patent number: 7750434Abstract: A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with: a bridge electrically connecting the first via and the second via; and a conductive pattern provided around the bridge, the outer edge of the conductive pattern being located outside the outer edge of the first wiring pattern and the second wiring pattern in the first wiring layer. The bridge functions as a coplanar line and suppresses generation of electromagnetic field.Type: GrantFiled: January 20, 2006Date of Patent: July 6, 2010Assignee: Sanyo Electric Co., Ltd.Inventors: Toshikazu Imaoka, Tetsuro Sawai, Atsushi Saita, Takeshi Yamaguchi, Makoto Tsubonoya, Kazunari Kurokawa
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Publication number: 20100018563Abstract: In the solar cell module 100, the resin adhesive 12 includes a plurality of removed portions 12a on the principal surface of the photoelectric conversion part 20 by removing the resin adhesive 12 in a vertical direction. The plurality of removed portions 12a are formed in the row in cross directions K.Type: ApplicationFiled: December 29, 2008Publication date: January 28, 2010Applicant: SANYO ELECTRIC CO., LTD.Inventors: Yukihiro Yoshimine, Hiroshi Kanno, Haruhisa Hashimoto, Atsushi Saita, Shigeharu Taira
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Publication number: 20090165850Abstract: The transparent conductive film 4 provided to the solar cell 10 includes the oxide of the first element ?, the second element ? doped into the oxide of the first element ?, and the third element ? doped into the oxide of the first element ?. The bond distance between the second element ? and oxygen O is shorter than the bond distance between the first element ? and oxygen O. The bond distance between the third element ? and oxygen O is longer than the bond distance between the first element ? and oxygen O.Type: ApplicationFiled: December 18, 2008Publication date: July 2, 2009Applicant: SANYO ELECTRIC CO., LTD.Inventors: Atsushi Saita, Akira Terakawa, Shigeo Yata
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Publication number: 20090032081Abstract: With the method for manufacturing the solar cell module according to the present embodiment, the width W1 of the connection region C in which the wiring member 11 and the connecting electrode 40 are electrically connected is set to be larger than the substantially half of the width W2 of the wiring member 11 in the thermocompression bonding process of the wiring member 11 using the resin adhesive 12 including the particles 13 onto the principal surface of the solar cell 10.Type: ApplicationFiled: August 1, 2008Publication date: February 5, 2009Applicant: SANYO ELECTRIC CO., LTD.Inventors: Atsushi Saita, Yukihiro Yoshimine, Shigeyuki Okamoto, Yasufumi Tsunomura, Shigeharu Taira, Hiroshi Kanno, Haruhisa Hashimoto
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Patent number: 7453153Abstract: The ground noise is reduced which propagates between circuit elements in a circuit device having a multiple stack structure. A grounding bonding pad provided on the surface of a second circuit element is connected to a bonding wire provided on the surface of a conduction layer via a grounding wire such as gold. A bonding pad provided on the surface of the conductive layer is connected to a lead provided on a ground wire via a grounding wire such as gold. This structure creates a capacitance between the second circuit element and the conduction layer so as to prevent the propagation of noise circuit from element to the ground wiring.Type: GrantFiled: March 29, 2006Date of Patent: November 18, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Atsushi Saita, Toshikazu Imaoka, Tetsuro Sawai, Yasunori Inoue
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Patent number: 7450397Abstract: A wiring board in which a line can be made narrower and/or a transmission loss can be reduced is developed. The wiring board includes a first conductor and a second conductor maintained at the same potential, a dielectric material layer provided between the first and second conductors, and a third conductor embedded in the dielectric material layer. In the wiring board, a thickness of the dielectric material layer in a first region located between the third conductor and the first conductor is larger than a thickness of the dielectric material layer in a second region located between the third conductor and the second conductor. Moreover, a cross-sectional shape of the third conductor is trapezoidal in which angles of respective ends of the third conductor on a side closer to the second conductor are obtuse.Type: GrantFiled: March 24, 2006Date of Patent: November 11, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Atsushi Saita, Toshikazu Imaoka, Tetsuro Sawai
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Publication number: 20060238961Abstract: The ground noise is reduced which propagates between circuit elements in a circuit device having a multiple stack structure. A grounding bonding pad provided on the surface of a second circuit element is connected to a bonding wire provided on the surface of a conduction layer via a grounding wire such as gold. A bonding pad provided on the surface of the conductive layer is connected to a lead provided on a ground wire via a grounding wire such as gold. This structure creates a capacitance between the second circuit element and the conduction layer so as to prevent the propagation of noise circuit from element to the ground wiring.Type: ApplicationFiled: March 29, 2006Publication date: October 26, 2006Inventors: Atsushi Saita, Toshikazu Imaoka, Tetsuro Sawai, Yasunori Inoue
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Publication number: 20060239102Abstract: The present invention discloses a power supply wiring method for stabilizing operation of a semiconductor integrated circuit device. A power supply mesh 24, which is arranged on an upper layer of a basic power supply wires 18 for supplying power to a logic circuit portion 13, includes vertical reinforcing power supply wires 22 and lateral reinforcing power supply wires 23. The widths of the vertical reinforcing power supply wires and lateral reinforcing power supply wires are optimized to mitigate IR drop or excessive current density in each division unit u0.Type: ApplicationFiled: February 26, 2004Publication date: October 26, 2006Inventors: Atsushi Saita, Mamoru Mukuno
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Publication number: 20060216484Abstract: A wiring board in which a line can be made narrower and/or a transmission loss can be reduced is developed. The wiring board includes a first conductor and a second conductor maintained at the same potential, a dielectric material layer provided between the first and second conductors, and a third conductor embedded in the dielectric material layer. In the wiring board, a thickness of the dielectric material layer in a first region located between the third conductor and the first conductor is larger than a thickness of the dielectric material layer in a second region located between the third conductor and the second conductor. Moreover, a cross-sectional shape of the third conductor is trapezoidal in which angles of respective ends of the third conductor on a side closer to the second conductor are obtuse.Type: ApplicationFiled: March 24, 2006Publication date: September 28, 2006Inventors: Atsushi Saita, Toshikazu Imaoka, Tetsuro Sawai
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Publication number: 20060170071Abstract: A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with: abridge electrically connecting the first via and the second via; and a conductive pattern provided around the bridge, the outer edge of the conductive pattern being located outside the outer edge of the first wiring pattern and the second wiring pattern in the first wiring layer. The bridge functions as a coplanar line and suppresses generation of electromagnetic field.Type: ApplicationFiled: January 20, 2006Publication date: August 3, 2006Inventors: Toshikazu Imaoka, Tetsuro Sawai, Atsushi Saita, Takeshi Yamaguchi, Makoto Tsubonoya, Kazunari Kurokawa