Patents by Inventor Atsushi SEKO
Atsushi SEKO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240153692Abstract: An inductor component includes an element assembly, a coil that is within the element assembly and is spirally wound in the coil axis direction, a first outer electrode electrically connected to one end of the coil, and a second outer electrode electrically connected to the other end of the coil. The element assembly includes an insulator, and a face of the element assembly includes a bottom face parallel to a coil axis direction, and a top face opposed to the bottom face in a height direction T orthogonal to the coil axis direction. The first and second outer electrodes each are exposed to at least the bottom face of the element assembly. The coil is formed by electrically interconnecting a plurality of coil wires laminated in the coil axis direction.Type: ApplicationFiled: October 17, 2023Publication date: May 9, 2024Applicant: Murata Manufacturing Co., Ltd.Inventor: Atsushi SEKO
-
Publication number: 20230420178Abstract: To suppress interference between an inductor component and other electronic components, in the inductor component, the distance from the first end surface to the surface of the first covering electrode in the direction perpendicular to the first end surface is defined as the thickness of the first covering electrode. On a second virtual line that passes through a geometric center of the first end surface and is perpendicular to a first main surface, a position where the thickness of the first covering electrode is maximum is shifted toward the first main surface side with respect to the geometric center of the first end surface.Type: ApplicationFiled: June 26, 2023Publication date: December 28, 2023Applicant: Murata Manufacturing Co., Ltd.Inventors: Atsushi SEKO, Masayuki YONEDA
-
Patent number: 10176916Abstract: A multilayer body is formed of a plurality of insulator layers that are stacked on top of one another. A coil is a helical coil provided in the multilayer body and includes a plurality of coil conductor layers that are superposed with one another so as to form a ring-shaped path when seen in plan view from a stacking direction and a plurality of via hole conductors that connect the plurality of coil conductor layers together. The path includes corners that project outward and corners that project inward. Each of the via hole conductors are provided at one of the corners, which project outward.Type: GrantFiled: January 16, 2013Date of Patent: January 8, 2019Assignee: Murata Manufacturing Co., Ltd.Inventors: Atsushi Seko, Katsuhiro Misaki
-
Patent number: 9653209Abstract: A method for producing an electronic component including a laminate, a circuit element provided therein, and external conductors electrically connected thereto. The method including steps of obtaining a mother laminate that has a plurality of the laminates arranged in a matrix-like state in a first direction and a second direction perpendicular thereto. The mother laminate is cut into the laminates. In the step of obtaining, the mother laminate is obtained such that the external conductors of two laminates adjacent in the first direction are joined, and circuit elements provided in the two laminates have a point-symmetrical relationship with each other. In the step of cutting, the mother laminate is cut along first cutoff lines extending in the second direction after the mother laminate is cut along second cutoff lines extending in the first direction. The external conductors are located on corresponding first cutoff lines.Type: GrantFiled: December 27, 2013Date of Patent: May 16, 2017Assignee: Murata Manufacturing Co., Ltd.Inventor: Atsushi Seko
-
Patent number: 9424980Abstract: A laminate in which plural insulator layers are stacked includes an external electrode that is exposed to the exterior of the laminate and includes a plurality of conductive layers stacked in a staking direction and passing through some of the plural insulator layers in the stacking direction. At least one side of the external electrode facing in the stacking direction is overlaid with rest of the plural insulator layers. At least one side surface of the external electrode facing in the stacking direction is uneven with another portion of the side surface.Type: GrantFiled: July 31, 2014Date of Patent: August 23, 2016Assignee: Murata Manufacturing Co., Ltd.Inventor: Atsushi Seko
-
Publication number: 20140375412Abstract: A laminate in which plural insulator layers are stacked includes an external electrode that is exposed to the exterior of the laminate and includes a plurality of conductive layers stacked in a staking direction and passing through some of the plural insulator layers in the stacking direction. At least one side of the external electrode facing in the stacking direction is overlaid with rest of the plural insulator layers. At least one side surface of the external electrode facing in the stacking direction is uneven with another portion of the side surface.Type: ApplicationFiled: July 31, 2014Publication date: December 25, 2014Applicant: MURATA MANUFACTURING CO., LTD.Inventor: Atsushi SEKO
-
Patent number: 8810350Abstract: A laminate in which plural insulator layers are stacked includes an external electrode that is exposed to the exterior of the laminate and includes a plurality of conductive layers stacked in a staking direction and passing through some of the plural insulator layers in the stacking direction. At least one side of the external electrode facing in the stacking direction is overlaid with rest of the plural insulator layers. At least one side surface of the external electrode facing in the stacking direction is uneven with another portion of the side surface.Type: GrantFiled: July 10, 2012Date of Patent: August 19, 2014Assignee: Murata Manufacturing Co., Ltd.Inventor: Atsushi Seko
-
Publication number: 20140224418Abstract: A method for producing an electronic component including a laminate, a circuit element provided therein, and external conductors electrically connected thereto. The method including steps of obtaining a mother laminate that has a plurality of the laminates arranged in a matrix-like state in a first direction and a second direction perpendicular thereto. The mother laminate is cut into the laminates. In the step of obtaining, the mother laminate is obtained such that the external conductors of two laminates adjacent in the first direction are joined, and circuit elements provided in the two laminates have a point-symmetrical relationship with each other. In the step of cutting, the mother laminate is cut along first cutoff lines extending in the second direction after the mother laminate is cut along second cutoff lines extending in the first direction. The external conductors are located on corresponding first cutoff lines.Type: ApplicationFiled: December 27, 2013Publication date: August 14, 2014Applicant: MURATA MANUFACTURING CO., LTD.Inventor: Atsushi SEKO
-
Publication number: 20130015937Abstract: A laminate in which plural insulator layers are stacked includes an external electrode that is exposed to the exterior of the laminate and includes a plurality of conductive layers stacked in a staking direction and passing through some of the plural insulator layers in the stacking direction. At least one side of the external electrode facing in the stacking direction is overlaid with rest of the plural insulator layers. At least one side surface of the external electrode facing in the stacking direction is uneven with another portion of the side surface.Type: ApplicationFiled: July 10, 2012Publication date: January 17, 2013Applicant: MURATA MANUFACTURING CO., LTD.Inventor: Atsushi SEKO