Patents by Inventor Atsushi Shirane

Atsushi Shirane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10340865
    Abstract: An amplifier of an embodiment includes: a plurality of input transistors of a plurality of differential pairs; a plurality of first resistance circuits mutually connecting respective sources of the input transistors corresponding to the differential pairs and mutually connecting the respective sources and reference potential points; a plurality of second resistance circuits being connected between the respective sources of the plurality of input transistors and the reference potential points, respectively; and a control circuit configured to generate a control signal controlling whether or not to electrically connect the plurality of first resistance circuits and the plurality of second resistance circuits to the respective sources of the input transistors.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: July 2, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Atsushi Shirane, Rui Ito, Toshiya Mitomo
  • Publication number: 20180358940
    Abstract: An amplifier of an embodiment includes: a plurality of input transistors of a plurality of differential pairs; a plurality of first resistance circuits mutually connecting respective sources of the input transistors corresponding to the differential pairs and mutually connecting the respective sources and reference potential points; a plurality of second resistance circuits being connected between the respective sources of the plurality of input transistors and the reference potential points, respectively; and a control circuit configured to generate a control signal controlling whether or not to electrically connect the plurality of first resistance circuits and the plurality of second resistance circuits to the respective sources of the input transistors.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Inventors: Atsushi Shirane, Rui Ito, Toshiya Mitomo
  • Publication number: 20180278220
    Abstract: An amplifier of an embodiment includes: a plurality of input transistors of a plurality of differential pairs; a plurality of first resistance circuits mutually connecting respective sources of the input transistors corresponding to the differential pairs and mutually connecting the respective sources and reference potential points; a plurality of second resistance circuits being connected between the respective sources of the plurality of input transistors and the reference potential points, respectively; and a control circuit configured to generate a control signal controlling whether or not to electrically connect the plurality of first resistance circuits and the plurality of second resistance circuits to the respective sources of the input transistors.
    Type: Application
    Filed: September 11, 2017
    Publication date: September 27, 2018
    Inventors: Atsushi Shirane, Rui Ito, Toshiya Mitomo
  • Patent number: 10084419
    Abstract: An amplifier of an embodiment includes: a plurality of input transistors of a plurality of differential pairs; a plurality of first resistance circuits mutually connecting respective sources of the input transistors corresponding to the differential pairs and mutually connecting the respective sources and reference potential points; a plurality of second resistance circuits being connected between the respective sources of the plurality of input transistors and the reference potential points, respectively; and a control circuit configured to generate a control signal controlling whether or not to electrically connect the plurality of first resistance circuits and the plurality of second resistance circuits to the respective sources of the input transistors.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Shirane, Rui Ito, Toshiya Mitomo