Abstract: A semiconductor integrated circuit comprises an electrically programmable fuse element that is provided between a programming voltage node and a latch node, and a latch circuit that latches a voltage at the latch node. The semiconductor integrated circuit further comprises a current source that controls a magnitude of an operation current of the latch circuit, and controls a resistance determination value for determining whether the fuse element is programmed or not.

Abstract: A semiconductor integrated circuit comprises an electrically programmable fuse element that is provided between a programming voltage node and a latch node, and a latch circuit that latches a voltage at the latch node. The semiconductor integrated circuit further comprises a current source that controls a magnitude of an operation current of the latch circuit, and controls a resistance determination value for determining whether the fuse element is programmed or not.

Abstract: A semiconductor device includes a first circuit block which operates on a first power supply voltage to output a first digital signal having an amplitude equal to that of the first power supply voltage, a level shifting circuit into which the first digital signal is input and which converts the amplitude of the first digital signal to an amplitude equal to that of a second power supply voltage to output as a second digital signal via an output terminal, a second circuit block which operates on the second power supply voltage and into which the second digital signal is input, and a monitor circuit which produces a first signal to set the output terminal of the level shifting circuit to a predetermined potential in a case where the first power supply voltage drops below a predetermined voltage level.

Abstract: A semiconductor memory device includes a first memory cell array, a plurality of bit lines, a plurality of word lines and a plate potential generating circuit. In the first memory cell array, a plurality of memory cells are arranged in a matrix, and respectively include memory cell transistors and memory cell capacitors which include first and second electrodes. The bit lines are connected to the first electrodes by the memory cell transistors, and the word lines are connected to gate electrodes of the memory cell transistors. The plate potential generating circuit applies a predetermined potential to each of the second electrodes, and is located on a first line from which memory cells on the both sides of the first memory cell array in a first direction in which the word lines extend are substantially equidistant.

Abstract: A semiconductor device includes a first circuit block which operates on a first power supply voltage to output a first digital signal having an amplitude equal to that of the first power supply voltage, a level shifting circuit into which the first digital signal is input and which converts the amplitude of the first digital signal to an amplitude equal to that of a second power supply voltage to output as a second digital signal via an output terminal, a second circuit block which operates on the second power supply voltage and into which the second digital signal is input, and a monitor circuit which produces a first signal to set the output terminal of the level shifting circuit to a predetermined potential in a case where the first power supply voltage drops below a predetermined voltage level.

Abstract: A semiconductor memory device having a plurality of bits includes an input buffer for receiving external data, a first write circuit for inputting a first control signal, and an output of the input buffer, and outputting the result on a first data line. A second write circuit inputs a second control signal and the result from the first data line, and outputs another output on a second data line. In a data writing operation, the second control signal is used commonly for at least two bits. The first write circuit sets the first data line to a fixed potential state when the first control signal is effective. In response to the fixed potential status on the first data line, the second write circuit sets the second data line to a potential state in which the second control signal is disregarded. A write per bit mode operation is controlled by controlling the second write circuit through a first data line.

Abstract: A semiconductor integrated circuit device having a high-efficiency transfer gate and which is applicable to a DRAM which has voltage-raised word lines configured from a data retention node, a data line that is precharged to a required level, a MOS transistor with the source and the drain each connected to a data line and a data retention node, a sense amplifier that amplifies the data that has been transferred to the data line via this MOS transistor a step-up circuit that applies a voltage that is higher than the drain voltage when compared with an absolute value, to the gate of the MOS transistor, and a step-down circuit for reducing the absolute value of a gate voltage of the MOS transistor at the timing of activation of the sense amplifier.