Abstract: An encoding apparatus employing both a CPU and a chip or circuit dedicated to the encoding is disclosed. The encoding apparatus includes a hardware encoder and a software encoder. The hardware encoder is configured by hardware dedicated to the encoding and encodes a portion of AV data. The software encoder encodes another portion of the AV data in parallel to the encoding process of the hardware encoder by the use of a CPU. A position detector detects a switching position of an allocation destination in the AV data. A data allocator allocates sections of the AV data divided by the switching position to both encoders. A synthesizer arranges the encoded AV data in a predetermined sequence to synthesize a series of encoded AV data. An output unit outputs the series of encoded AV data.

Abstract: A card (1) to be mechanically connected with a socket (21,22,23,24,25) of an interface bus of a type selectable from among a plurality of bus widths. The card (1) includes an electrical connection portion (150) to be electrically connected with the socket of the interface bus, and a connection reinforcing portion (170) to reinforce a mechanical connection with the socket of the interface bus, wherein the connection reinforcing portion (170) is at least partially removable.

Abstract: A data conversion system for converting data outputted from an information processor into data in a different format in real time while preventing any defect of an image such as frame missing or frame repetition of moving image data by synchronizing data transfer with converted data output. One of first and second nodes on an IEEE1394 bus functions as a cycle master, and first data is transferred from the first node to the second node in synchronism with a cycle start packet outputted from the cycle master. Second data generated by converting the first data by the second node is outputted in synchronism with a reference signal inputted from outside.

Abstract: A transmitting apparatus for transmitting transmission data to a receiving apparatus is disclosed which includes: means for obtaining apparatus information of the receiving apparatus; a source of video data and its auxiliary data; means for determining whether or not to synthesize the video data and the auxiliary data with each other, based on the obtained apparatus information; means for synthesizing, according to the above determination, the video data and frame data which is the auxiliary data associated with a frame of the video data, to generate the transmission data, wherein the frame data is included in a video data arranging area of the video data; and means for transmitting the transmission data to the receiving apparatus. Furthermore, a receiving apparatus is also disclosed which extracts the frame data from the video data arranging area of received data.

Abstract: A card (1) to be mechanically connected with a socket (21,22,23,24,25) of an interface bus of a type selectable from among a plurality of bus widths. The card (1) includes an electrical connection portion (150) to be electrically connected with the socket of the interface bus, and a connection reinforcing portion (170) to reinforce a mechanical connection with the socket of the interface bus, wherein the connection reinforcing portion (170) is at least partially removable.

Abstract: An encoding apparatus employing both a CPU and a chip or circuit dedicated to the encoding is disclosed. The encoding apparatus includes a hardware encoder and a software encoder. The hardware encoder is configured by hardware dedicated to the encoding and encodes a portion of AV data. The software encoder encodes another portion of the AV data in parallel to the encoding process of the hardware encoder by the use of a CPU. A position detector detects a switching position of an allocation destination in the AV data. A data allocator allocates sections of the AV data divided by the switching position to both encoders. A synthesizer arranges the encoded AV data in a predetermined sequence to synthesize a series of encoded AV data. An output unit outputs the series of encoded AV data.

Abstract: A data conversion system for converting data output from an information processor into data in a different format in real time while preventing image defects such as dropped frames or repeated frames in moving image data by synchronizing data transfer with converted data output. One of first and second nodes on an IEEE1394 bus functions as a cycle master, and first data is transferred from the first node to the second node in synchronism with a cycle start packet outputted from the cycle master. Second data generated by converting the first data by the second node is outputted in synchronism with an external reference signal. The system includes an external synchronizing signal receiver for receiving an external reference signal provided on at least one of the first and second nodes, and a synchronization adjustment unit for synchronizing the frequency of the cycle start packet output from the cycle master with the frequency of the reference signal received by the external synchronizing signal receiver.