Patents by Inventor Atsushi TERAI

Atsushi TERAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220393015
    Abstract: Provided is a semiconductor device in which a leakage current is reduced, the semiconductor device which is particularly useful for power devices. A semiconductor device including at least: an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component; an n?-type semiconductor layer that is placed on the n+-type semiconductor layer, the n?-type semiconductor layer containing a crystalline oxide semiconductor as a major component; a high-resistance layer with at least a part thereof being embedded in the n?-type semiconductor layer, the high-resistance layer having a bottom surface located at a distance of less than 1.5 ?m from an upper surface of the n+-type semiconductor layer; and a Schottky electrode that forms a Schottky junction with the n?-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 8, 2022
    Inventors: Mitsuru OKIGAWA, Fujio OKUI, Yasushi HIGUCHI, Koji AMAZUTSUMI, Hidetaka SHIBATA, Yuji KATO, Atsushi TERAI
  • Publication number: 20220393037
    Abstract: Provided is a semiconductor device in which a leakage current is reduced, the semiconductor device which is particularly useful for power devices. A semiconductor device including at least: an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component; an n?-type semiconductor layer that is placed on the n+-type semiconductor layer, the n?-type semiconductor layer containing a crystalline oxide semiconductor as a major component; a high-resistance layer with at least a part thereof being embedded in the n?-type semiconductor layer, a depth d (?m) of the part embedded in the n?-type semiconductor layer satisfying d?1.4; and a Schottky electrode that forms a Schottky junction with the n?-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 8, 2022
    Inventors: Mitsuru OKIGAWA, Fujio OKUI, Yasushi HIGUCHI, Koji AMAZUTSUMI, Hidetaka SHIBATA, Yuji KATO, Atsushi TERAI