Abstract: A second memory has n banks accessible in parallel, and stores pixel data. An input DMA controller respectively transfers the pixel data stored in the second memory to n multiply-accumulate units by using n input channels. A sequence controller controls the input DMA controller so as to cause a first input channel to transfer the pixel data in a first pixel space of the input bank to a first multiply-accumulate unit and cause a second input channel to transfer the pixel data in a second pixel space of the same input bank to a second multiply-accumulate unit.

Abstract: A storage means access control method for an NC system, which has no adverse effect on the execution of an NC instruction. The NC system has a first storage means and a second storage means having an access time longer than that of the first storage means, and sequentially executes NC instructions in blocks of an NC program stored in the first storage means, block by block. The NC instructions in the blocks of the NC program are previously classified into waitable instructions and unwaitable instructions. When there is a request for access to the second storage means during execution of the NC program, if an NC instruction in an execution block to be executed subsequently is a waitable instruction, access to the second storage means is executed after the NC instruction in the execution block has been executed. If the NC instruction in the execution block is an unwaitable instruction, access to the second storage means is not executed after the NC instruction in the execution block has been executed.