Abstract: An occupant restraint system of the present invention includes a curtain airbag (2), a side airbag (4), a seat belt (6) with a built-in pretensioner, and a rollover detection device (11) configured to detect or predict rollover of a vehicle (1). The occupant restraint system further includes a control device (11) configured to perform control of deploying the side airbag when the rollover of the vehicle is detected or predicted by the rollover detection device, activating the pretensioner (19) after a predetermined time elapses from the deployment of the side airbag, and then deploying the curtain airbag.

Abstract: A main memory stores cache blocks obtained by dividing a program. At a position in a cache block where a branch to another cache block is provided, an instruction is embedded for activating a branch resolution routine for performing processing, such as loading of a cache block of the branch target. A program is loaded into a local memory in units of cache blocks, and the cache blocks are serially stored in first through nth banks, which are sections provided in the storage area. Management of addresses in the local memory or processing for discarding a copy of a cache block is performed with reference to an address translation table, an inter-bank reference table, and a generation number table.

Abstract: An occupant restraint system of the present invention includes a curtain airbag (2), a side airbag (4), a seat belt (6) with a built-in pretensioner, and a rollover detection device (11) configured to detect or predict rollover of a vehicle (1). The occupant restraint system further includes a control device (11) configured to perform control of deploying the side airbag when the rollover of the vehicle is detected or predicted by the rollover detection device, activating the pretensioner (19) after a predetermined time elapses from the deployment of the side airbag, and then deploying the curtain airbag.

Abstract: A program stored in a memory is read, and in a path representing the order of processing instruction sequences forming the program, a subgraph including a sequence of instructions that includes only one instruction at the entry and only one instruction at the exit is identified. At least a part of a source instruction sequence included in the subgraph is extracted as a new program block and stored in a memory. An instruction for calling the instruction sequence in the new program block is inserted in a program block including the source instruction sequence. The program block including the source instruction sequence is then stored in the memory.

Abstract: An improved interrupt control mechanism is provided in a system in which a plurality of OS's (OS's) are concurrently operating. In the system, a main OS executing an interrupt control process is set up, sub OS's other than the main OS are not provided with a right to determine an interrupt mask, the sub OS notifies the main OS whether the sub OS is in an interrupt enabled state or an interrupt disabled state, and the main OS performs an interrupt mask control process based on the notified information. In this arrangement, an inconvenience that an interrupt process is reserved due to a mask control performed by the sub OS itself is corrected, the main OS can perform the interrupt control as the main OS intends, and a required interrupt process can be performed with priority. Memory area is saved because a vector area of the sub OS is managed by the main OS.

Abstract: An information processing apparatus includes a control operating system executing a process for allocating a plurality of logical processors to a physical processor in a time division manner, and a guest operating system for which a logical partition as an application entity of the logical processor is set. The control operating system sets and updates, as address conversion tables for determining an allocation relationship between the logical processor and the physical processor, two address conversion tables of a first conversion table that sets an allocation relationship between a logical partition address space and a physical address space and a second conversion table that sets an allocation relationship between a virtual address space in the guest operating system and the physical address space.

Abstract: A main memory stores cache blocks obtained by dividing a program. At a position in a cache block where a branch to another cache block is provided, there is embedded an instruction for activating a branch resolution routine for performing processing, such as loading of a cache block of the branch target. A program is loaded into a local memory in units of cache blocks, and the cache blocks are serially stored in first through nth banks, which are sections provided in the storage area. Management of addresses in the local memory or processing for discarding a copy of a cache block is performed with reference to an address translation table, an inter-bank reference table and a generation number table.

Abstract: In process control based on partition setting which is a process corresponding to a plurality of operating systems (OSs), a configuration is implemented in which an interrupt request can be processed efficiently. In process control for switching processes which are based on the plurality of OSs, it is configured to set an interrupt processing partition as an interrupt processing execution period corresponding to an interrupt processing request so as to coincide with a pre-set partition switching timing. Further, a processing schedule is set, taking a maximum allowable delay time, a minimum allowable delay time into account. As a result of the present configuration, an increment in the number of partition switching processes can be kept to 1, and thus efficient data processing becomes possible.

Abstract: An information processing apparatus includes a thread management unit managing thread information on a per data processing unit basis, and a memory area management unit managing a memory area. The thread management unit stores a thread list containing entry time information that is recorded on a per thread basis as function call time of an operating system from a data processing program. The memory area management unit stores a release queue containing release request time that is recorded on an area unit basis concerning an unreleased memory area in response to a release request, compares the release request time set in each queue component contained in the release queue with the oldest entry time of each queue component in the thread list during a memory area allocation process, and allocates the memory area to the queue component having the release request time set prior to the oldest entry time.

Abstract: A mechanism for recording a timing in which a high urgency process is started is provided, and upon entry to a critical section in the middle of a low urgency process, by referencing the record, it is inspected whether a high urgency process will be started during execution of the critical section. If it will not be started, the critical section is entered, and if it will be started, control is exerted so that entry to the critical section is postponed until the high urgency process is completed. Exclusive access control in a critical section can be performed suitably under conditions where a plurality of task execution environments exist.

Abstract: A program stored in a memory is read, and in a path representing the order of processing instruction sequences forming the program, a subgraph including a sequence of instructions that includes only one instruction at the entry and only one instruction at the exit is identified. At least a part of a source instruction sequence included in the subgraph is extracted as a new program block and stored in a memory. An instruction for calling the instruction sequence in the new program block is inserted in a program block including the source instruction sequence. The program block including the source instruction sequence is then stored in the memory.

Abstract: A main memory stores cache blocks obtained by dividing a program. At a position in a cache block where a branch to another cache block is provided, there is embedded an instruction for activating a branch resolution routine for performing processing, such as loading of a cache block of the branch target. A program is loaded into a local memory in units of cache blocks, and the cache blocks are serially stored in first through nth banks, which are sections provided in the storage area. Management of addresses in the local memory or processing for discarding a copy of a cache block is performed with reference to an address translation table, an inter-bank reference table and a generation number table.

Abstract: A main memory stores cache blocks obtained by dividing a program. At a position in a cache block where a branch to another cache block is provided, there is embedded an instruction for activating a branch resolution routine for performing processing, such as loading of a cache block of the branch target. A program is loaded into a local memory in units of cache blocks, and the cache blocks are serially stored in first through nth banks, which are sections provided in the storage area. Management of addresses in the local memory or processing for discarding a copy of a cache block is performed with reference to an address translation table, an inter-bank reference table and a generation number table.

Abstract: An improved interrupt control mechanism is provided in a system in which a plurality of OS's (OS's) are concurrently operating. In the system, a main OS executing an interrupt control process is set up, sub OS's other than the main OS are not provided with a right to determine an interrupt mask, the sub OS notifies the main OS whether the sub OS is in an interrupt enabled state or an interrupt disabled state, and the main OS performs an interrupt mask control process based on the notified information. In this arrangement, an inconvenience that an interrupt process is reserved due to a mask control performed by the sub OS itself is corrected, the main OS can perform the interrupt control as the main OS intends, and a required interrupt process can be performed with priority. Memory area is saved because a vector area of the sub OS is managed by the main OS.

Abstract: A task management system that inherit priority and that can reduce the queue operation required for transition to/return from a mutual exclusion awaiting state The task management system can execute a task without considering its priority, start or stop a server task and inherit priority without operating the dispatch queue. The task management system includes activity retaining information, context retaining information, and a dispatch queue used to select the highest priority task. Information on a task is divided and managed by the activity and the context, where each activity is inserted into/deleted from the dispatch queue. When the priority of a task is inherited by another task, only the correspondence between activity and context is changed.

Abstract: An information processing apparatus includes a control operating system executing a process for allocating a plurality of logical processors to a physical processor in a time division manner, and a guest operating system for which a logical partition as an application entity of the logical processor is set. The control operating system sets and updates, as address conversion tables for determining an allocation relationship between the logical processor and the physical processor, two address conversion tables of a first conversion table that sets an allocation relationship between a logical partition address space and a physical address space and a second conversion table that sets an allocation relationship between a virtual address space in the guest operating system and the physical address space.

Abstract: An information processing apparatus includes a thread management unit managing thread information on a per data processing unit basis, and a memory area management unit managing a memory area. The thread management unit stores a thread list containing entry time information that is recorded on a per thread basis as function call time of an operating system from a data processing program. The memory area management unit stores a release queue containing release request time that is recorded on an area unit basis concerning an unreleased memory area in response to a release request, compares the release request time set in each queue component contained in the release queue with the oldest entry time of each queue component in the thread list during a memory area allocation process, and allocates the memory area to the queue component having the release request time set prior to the oldest entry time.

Abstract: A system capable of changing an operating frequency and a power source voltage of a processor, the operating frequency of the processor necessary for processing a periodic real-time task and a non-real-time task at the same time as an optimum value of the power source voltage for the processor is determined to be responding to the operating frequency changing with time, so as to diminish the power consumption of the processor, as the application's real-time request is met.

Abstract: In process control based on partition setting which is a process corresponding to a plurality of operating systems (OSs), a configuration is implemented in which an interrupt request can be processed efficiently. In process control for switching processes which are based on the plurality of OSs, it is configured to set an interrupt processing partition as an interrupt processing execution period corresponding to an interrupt processing request so as to coincide with a pre-set partition switching timing. Further, a processing schedule is set, taking a maximum allowable delay time, a minimum allowable delay time into account. As a result of the present configuration, an increment in the number of partition switching processes can be kept to 1, and thus efficient data processing becomes possible.

Abstract: A secure connection between the main unit of a portable information device and a peripheral device via a wireless network is ensured by using an electronic seal that makes it possible to transmit an encryption key to the portable information terminal and the peripheral device thereof by an operation which is analogous to “seal affixing” by a user confirmed as an authorized user. For example, user confirmation is performed by an authentication technology using biometric information, such as “fingerprint authentication”. After the portable information terminal and the peripheral device thereof perform mutual recognition, they can perform secure mutual communication via a wireless network, etc., by using the encryption key provided via the electronic seal.