Abstract: According to one embodiment, a semiconductor device c includes: a package substrate including a base including a mount portion, and terminals; a semiconductor chip including a first pad to which a ground voltage is supplied, a second pad electrically connected to a first terminal among the terminals, and a semiconductor circuit connected to the first and second pads, the semiconductor chip being provided above the mount portion; and a first capacitor chip including a first capacitor unit provided in a silicon substrate, a first node supplied with the ground voltage, and a second node electrically connected to the second pad, the first capacitor chip being provided above the mount portion.

Abstract: According to the embodiments, a core block is formed on a semiconductor chip, and is constructed of an integrated circuit that can operate independently. A power-supply switch is formed on the semiconductor chip, and connects or disconnects the core block to or from a power line. A capacitor is formed on the semiconductor chip, and is connected to the power line in parallel to the core block. A selection switch is formed on the semiconductor chip, and connects or disconnects the capacitor to or from the power line.

Abstract: A test facilitating circuit is contained in a FPGA-GATE ARRAY. In the gate array chip there are disposed I/O cells, a boundary scan circuit, a controller and an internal circuit. The arrangement of the external terminals of a package is the same as the arrangement of the external terminals of the FPGA. The test terminal corresponds to the data program terminal of the FPGA. When the FPGA is displaced with a gate array, the data program terminal of the FPGA becomes unnecessary and is used as a control terminal for the boundary scan circuit. The position of the test terminal is fixed, thereby to achieve a facilitated, automated and standardized design.

Abstract: A test facilitating circuit is contained in a FPGA-GATE ARRAY. In the gate array chip there are disposed I/O cells, a boundary scan circuit, a controller and an internal circuit. The arrangement of the external terminals of a package is the same as the arrangement of the external terminals of the FPGA. The test terminal corresponds to the data program terminal of the FPGA. When the FPGA is displaced with a gate array, the data program terminal of the FPGA becomes unnecessary and is used as a control terminal for the boundary scan circuit. The position of the test terminal is fixed, thereby to achieve a facilitated, automated and standardized design.