Abstract: Provided is an antenna device capable of simplifying a structure while preventing degradation of antenna performance even with an upright type double-case structure. An antenna device having a double-case structure includes an inner case inside of which a housing space is formed so as to house a coil element and the like therein, the inner case being covered with an outer case. An antenna element is provided between an outer surface of the inner case and an inner surface of the outer case. The antenna element is electrically connected to the coil element provided in the housing space while keeping water-tightness of the housing space.

Abstract: An antenna unit includes a base having a base-side fitting portion, antenna elements disposed on the base, an inner case fixed to the base and covering the antenna elements, and an outer case mounted on the base covering the inner case. The outer case 50 has an outer-case-side fitting portion fitted to the base-side fitting portion.

Abstract: Provided is an antenna device capable of simplifying a structure while preventing degradation of antenna performance even with an upright type double-case structure. An antenna device having a double-case structure includes an inner case inside of which a housing space is formed so as to house a coil element and the like therein, the inner case being covered with an outer case. An antenna element is provided between an outer surface of the inner case and an inner surface of the outer case. The antenna element is electrically connected to the coil element provided in the housing space while keeping water-tightness of the housing space.

Abstract: An antenna unit includes a base having a base-side fitting portion, antenna elements disposed on the base, an inner case fixed to the base and covering the antenna elements, and an outer case mounted on the base covering the inner case. The outer case 50 has an outer-case-side fitting portion fitted to the base-side fitting portion.

Abstract: A data processing apparatus is provided which allows easy identification of a correspondence relationship between a trace packet and a performance packet. The data processing apparatus includes: a measurement trigger generation unit that generates a measurement trigger; a performance monitor unit that measures a performance measurement event collected from a central processing unit (CPU) and outputs a measurement value; and a CPU trace unit that generates a trace packet sequence of trace information including an operation record of the CPU. Upon receipt of the measurement trigger, the performance monitor unit starts or ends measurement of performance metrics or outputs the measurement value, while, upon receipt of the measurement trigger, the CPU trace unit generates a trigger packet indicating generation of the measurement trigger and inserts the trigger packet, at a position corresponding to timing with which the measurement trigger is generated, into the trace packet sequence.

Abstract: Overhead is significant when a timestamp according to a reference time is inserted. In view of this, there is provided an LSI which includes: a first time information conversion unit which converts, into time information of a reference time, time information from a first trace data source; a second time information conversion unit which converts, into time information of a reference time, time information from a second trace data source; and a packet merging unit.

Abstract: A processor performance analysis device analyzes performance of a multithreaded processor in a system LSI which includes: the multithreaded processor which executes processing in parallel using multiple logical processors; a functional core which executes processing different from the processing executed by the multithreaded processor; and a memory interface which receives each access request and controls access to memory. The processor performance analysis device includes: an operational information output unit which monitors the multithreaded processor to output operational information; an access information output unit which monitors the memory interface to output memory access information; and an analysis information output unit which analyzes the performance of the multithreaded processor using the operational information and the memory access information.

Abstract: States of LSI internal signals (100 to 107) are monitored. Signal name information (31), signal state information (32), and information (33) about time in an LSI when a signal undergoes a state transition, are packetized and output as trace information (10) to the outside. In a development supporting device, the trace information (10) is decoded, the time information of the LSI is converted into real-time information, and based on the resultant information, a waveform of an LSI internal signal is reproduced. A plurality of LSI internal signals can be traced using terminals (16) the number of which is smaller than the number of the signals to be traced.

Abstract: When a call instruction or interrupt branch is executed by a CPU, its return address is pushed to a stack memory. When a return instruction is executed, the pushed return address is popped from the stack memory. When a return instruction is executed by the CPU, a comparator compares the branch address output from the CPU and the address output from the stack memory. As a result of the comparison, if the addresses match, the branch address is not output as trace information. If the addresses do not match, the address register receives the branch address from the CPU and outputs the received branch address as the trace information.

Abstract: A debugging system which can efficiently obtain debugging information and which has excellent debugging efficiency is a debugging system which stops execution of a program executed in a program executing apparatus, at a break point, and assists debugging of the program, and which includes: a dump control unit configured to dump information indicating an operating state of the program executing apparatus, at plural points in time prior to the stopping of the execution of the program; and a dump information accumulating unit configured to accumulate the information indicating the operating state of the program executing apparatus dumped by said dump control unit.

Abstract: A processor includes a statically scheduled command removal unit which removes a statically scheduled command upon receiving a command issuing signal, a command execution condition establishing signal, and a statically scheduled execution determination signal that indicates a command for which execution is determined in advance, an encoding unit which encodes an execution history for commands, statically scheduled commands excluded, upon receiving a command execution condition establishing signal, for which a statically scheduled command is excluded, and a command issue signal, for which a statically scheduled command is excluded, all of which are obtained by the statically scheduled command removal unit, and a data packet generation unit which generates a trace packet upon receiving encoded data obtained by the encoding unit. This trace information is processed by a development supporting apparatus.

Abstract: When a call instruction or interrupt branch is executed by a CPU, its return address is pushed to a stack memory. When a return instruction is executed, the pushed return address is popped from the stack memory. When a return instruction is executed by the CPU, a comparator compares the branch address output from the CPU and the address output from the stack memory. As a result of the comparison, if the addresses match, the branch address is not output as trace information. If the addresses do not match, the address register receives the branch address from the CPU and outputs the received branch address as the trace information.

Abstract: A semiconductor integrated circuit device includes: a first semiconductor chip including a CPU and a debug basic circuit section for verifying operation of a program executed by the CPU; and a second semiconductor chip retained over a principal surface of the first semiconductor chip and including a debug extension circuit section electrically connected to the CPU and the debug basic circuit section. The debug basic circuit section includes a debug command analyzing section for analyzing a command input from outside. The debug extension circuit section formed in the second semiconductor chip includes a debugging function circuit section including at least one debug circuit.

Abstract: A semiconductor integrated circuit device includes: a first semiconductor chip including a CPU and a debug basic circuit section for verifying operation of a program executed by the CPU; and a second semiconductor chip retained over a principal surface of the first semiconductor chip and including a debug extension circuit section electrically connected to the CPU and the debug basic circuit section. The debug basic circuit section includes a debug command analyzing section for analyzing a command input from outside. The debug extension circuit section formed in the second semiconductor chip includes a debugging function circuit section including at least one debug circuit.

Abstract: The present invention provides a debug apparatus that can set complex break conditions, minimize a time lag from the detection of a break event to the break an execution of a program, and has a debug function with a necessary minimized break determinator included in a chip. A part of the break conditions in a sequence is set in an external break determinator. The remaining condition other than the part of the conditions is set in an internal break determinator. While monitoring an operation status of a processor executing a program, when the conditions set in the external break determinator are satisfied, a break enable signal is input to an AND logic circuit via a break enable input terminal and is held. When the break determinator detects the satisfaction of the remaining condition stored in the internal break determinator, a break signal is supplied from the AND logic circuit to the CPU, thereby breaking the program without delay.

Abstract: There is provided a correlation degree operation apparatus in which the search area is readily extensible, in which a high-speed process can be assured even though the search area is extended, and which can be formed in a simple arrangement. The search area memory stores the picture element data of a search area including ((m.times.M).times.L) candidate blocks. The correlation degree operation unit executes an operation of a degree of correlation between a reference picture block and each of the candidate blocks, with the use of picture element data supplied from the search area memory, this operation being executed by a pipeline process for each candidate block group composed of (M.times.L) candidate blocks. The search area memory has the function of supplying four picture element data at the same clock cycle. This enables the correlation degree operation unit to continuously execute the pipeline processes for the candidate block groups.

Abstract: The address generation unit 166 generates a write address for each picture data to be written in the frame memory 169. The memory control unit 165 writes picture data which have the same Y address and consecutive X addresses to the first bank and the second bank alternately per one-page mode length, and further writes picture data which have the same X address and adjacent Y addresses to the different banks. The memory control unit 165 determines a minimum area which consists of an odd number of page mode lengths and includes picture data of a square area having the same Y address, and reads the determined area from the two storage areas alternately per Y address.

Abstract: The address generation unit 166 generates a write address for each picture data to be written in the frame memory 169. The memory control unit 165 writes picture data which have the same Y address and consecutive X addresses to the first bank and the second bank alternately per one-page mode length, and further writes picture data which have the same X address and adjacent Y addresses to the different banks. The memory control unit 165 determines a minimum area which consists of an odd number of page mode lengths and includes picture data of a square area having the same Y address, and reads the determined area from the two storage areas alternately per Y address.