Patents by Inventor Atsushi Ueno

Atsushi Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030216018
    Abstract: The reduction of length of a gate electrode is suppressed in the process of thinning it. A hard mask (5a) is thinned and used to etch a gate electrode material film (4) to form a gate electrode. At this time, a resist mask (10) having an opening (11) over an active region (1) is formed; the resist mask (10) covers at least both ends in the length direction of the hard mask (5a) and exposes in the opening (11) at least the entirety of the part of the hard mask (5a) which lies right above the active region (1). The hard mask (5a) is thinned by etching using the resist mask (10) as a mask and therefore the hard mask (5a) is thinned in the part over the active region (1) without being shortened in the length direction. As a result, the gate electrode formed by using the thinned hard mask (5a) is not shortened in length.
    Type: Application
    Filed: November 21, 2002
    Publication date: November 20, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Tetsuya Yamada, Atsushi Ueno, Kouichirou Tsujita, Atsumi Yamaguchi, Takashi Okagawa
  • Publication number: 20030186741
    Abstract: A small screen which enables a player to easily grasp the situation of a game field as well as the positional relationship between the game objects is displayed on a game screen in a game device.
    Type: Application
    Filed: March 28, 2002
    Publication date: October 2, 2003
    Applicant: Kabushiki Kaisha Sega Enterprises, Ltd.
    Inventors: Yasuhiro Hayashida, Atsushi Ueno, Taishi Yasuda
  • Patent number: 6617080
    Abstract: The present invention provides a photomask, a semiconductor device, and a method for exposing through the photomask. The photomask comprises a photomask substrate, and an on-mask circuit area including an on-mask circuit pattern and an on-mask test mark area including an on-mask test pattern, both formed on the surface of the substrate, wherein the photomask substrate further includes an on-mask photolithography screening mark area including an on-mask comparison pattern and an on-mask screening pattern, the on-mask comparison pattern has substantially the same configuration as at least a part of the on-mask circuit pattern, and the on-mask screening pattern has substantially the same configuration as at least a part of the on-mask test pattern. The present invention allows it to measure the actual displacement generated from an overlaying (i.e. alignment) process for the purpose of eliminating of an the overlay displacement which can take place in a photolithography process.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: September 9, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihide Kawachi, Takuya Matsushita, Shigenori Yamashita, Yuki Miyamoto, Atsushi Ueno, Shinroku Maejima
  • Publication number: 20030127751
    Abstract: An alignment mark structure according to the present invention includes alignment marks (8) and underlying layers (5) arranged under the alignment marks (8). The underlying layers (5) each form a line for defining a pattern. A metal diffusion preventing and etching stopper layer (6) is interposed between the underlying layers (5) and the alignment marks (8). As the underlying layers (5) each form a line, dishing therein can be suppressed even when the underlying layers (5) are formed through a damascene process. As a result, there occurs no difference in level between the alignment marks (8) that may result in deterioration in alignment accuracy. Further, due to existence of the metal diffusion preventing and etching stopper layer (6), metallic material for forming the underlying layers (5) can be prevented from diffusing resulting from a thermal processing, for example.
    Type: Application
    Filed: July 25, 2002
    Publication date: July 10, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Tetsuya Yamada, Atsushi Ueno
  • Publication number: 20020100978
    Abstract: A mark structure (100) consists of a gate oxide film (102) formed on a semiconductor substrate (101), a gate wiring layer (103) formed on the gate oxide film (102), an insulating film (104) formed on the gate wiring layer (103) and a sidewall (105) formed in contact with side surfaces of the insulating film (104), the gate wiring layer (103) and the gate oxide film (102). An opaque bit line layer (113) is formed of a polycide consisting of a doped polysilicon layer (1131) and a tungsten silicide layer (1132), extending from on the interlayer insulating film (107) to on the mark structure (100). With this structure, a semiconductor device which allows measurement of alignment mark and overlay check mark with high precision in a lithography process, has no structure unnecessary for a mark and suppresses creation of extraneous matter in a process of manufacturing a semiconductor device to prevent deterioration in manufacturing process yield and a method of manufacturing the semiconductor device can be provided.
    Type: Application
    Filed: February 25, 2002
    Publication date: August 1, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Kazuo Tomita, Atsushi Ueno
  • Patent number: 6409596
    Abstract: A small screen which enables a player to easily grasp the situation of a game field as well as the positional relationship between the game objects is displayed on a game screen in a game device. A game device which displays on a monitor screen a picture of a game being proceeded in a virtual space by a first object controlled by a player and a second object controlled by a computer comprises a supplementary screen forming means (S210) for forming on the monitor screen a small screen showing the surrounding condition with the first object in the center, a distance calculating means (S202) for calculating the distance between the first object and the second object in the virtual space, and a display magnification setting means (S208) for setting the display magnification on the small screen in correspondence with the distance between the above objects.
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: June 25, 2002
    Assignee: Kabushiki Kaisha Sega Enterprises
    Inventors: Yasuhiro Hayashida, Atsushi Ueno, Taishi Yasuda
  • Patent number: 6376924
    Abstract: A mark structure (100) consists of a gate oxide film (102) formed on a semiconductor substrate (101), a gate wiring layer (103) formed on the gate oxide film (102), an insulating film (104) formed on the gate wiring layer (103) and a sidewall (105) formed in contact with side surfaces of the insulating film (104), the gate wiring layer (103) and the gate oxide film (102). An opaque bit line layer (113) is formed of a polycide consisting of a doped polysilicon layer (1131) and a tungsten silicide layer (1132), extending from on the interlayer insulating film (107) to on the mark structure (100). With this structure, a semiconductor device which allows measurement of alignment mark and overlay check mark with high precision in a lithography process, has no structure unnecessary for a mark and suppresses creation of extraneous matter in a process of manufacturing a semiconductor device to prevent deterioration in manufacturing process yield and a method of manufacturing the semiconductor device can be provided.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: April 23, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuo Tomita, Atsushi Ueno
  • Publication number: 20010048145
    Abstract: A semiconductor device enabling precise and accurate measurement of an inspection mark in a simple manner is obtained. The semiconductor device includes a device forming area and a dicing line area arranged to surround the device forming area on a semiconductor substrate. In the dicing line area, first and second registration marks formed in different shots are provided, and the first and second registration marks include auxiliary marks for identifying the first and second registration marks.
    Type: Application
    Filed: November 30, 2000
    Publication date: December 6, 2001
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masahiko Takeuchi, Koichiro Narimatsu, Atsushi Ueno
  • Publication number: 20010045620
    Abstract: An improved method for producing a semiconductor device in which overpolishing is prevented at a chemical mechanical polishing time to eliminate the influence of peripheries on the object part. A plasma oxide film is formed on a semiconductor substrate so as to fill a recess and a trench. With the use of a resist film as a mask, the plasma oxide film is selectively etched to leave an overpolish-preventing support member in a neighborhood of the recess, which is a photo-related mark, for providing a support against overpolishing at a chemical mechanical polishing time. The surface of the semiconductor substrate is polished by chemical mechanical polishing. Thereafter, a nitride film and an oxide film are removed.
    Type: Application
    Filed: February 26, 2001
    Publication date: November 29, 2001
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshitaka Fujiishi, Atsushi Ueno
  • Patent number: 5879843
    Abstract: A method of reducing a registration error is provided in which the registration error can be uniformly distributed even if an amount of displacement is larger than others at only one of a plurality of measuring points. According to the method, amounts of displacement are measured first at a plurality of measuring points, then one half the sum of the maximum value and the minimum value of the measured amounts of displacement is calculated to obtain a correction value. The correction value is fed back to an exposure apparatus as a correction value for an exposure condition setting file within the exposure apparatus used in an exposure step. The registration error can be distributed uniformly even if amounts of displacement at a plurality of measuring points are considerably different from each other.
    Type: Grant
    Filed: January 15, 1998
    Date of Patent: March 9, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Atsushi Ueno
  • Patent number: 5731113
    Abstract: A method of reducing a registration error is provided in which the registration error can be uniformly distributed even if an amount of displacement is larger than others at only one of a plurality of measuring points. According to the method, amounts of displacement are measured first at a plurality of measuring points, then one half the sum of the maximum value and the minimum value of the measured amounts of displacement is calculated to obtain a correction value. The correction value is fed back to an exposure apparatus as a correction value for an exposure condition setting file within the exposure apparatus used in an exposure step. The registration error can be distributed uniformly even if amounts of displacement at a plurality of measuring points are considerably different from each other.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: March 24, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Atsushi Ueno
  • Patent number: 5669718
    Abstract: A steering column bearing is comprised of an outer bush and an inner bush held in the outer bush. The outer bush includes: an inner ring having a lip portion and a retaining protrusion formed projectingly along the circumferential direction at a predetermined interval from the lip portion in an axial direction; an outer ring having protrusions; a support leg by which an outer peripheral surface portion of the inner ring not corresponding to a hollow cylindrical recess and an inner peripheral surface portion of the outer ring corresponding to that outer peripheral surface portion are integrally connected to each other in the circumferential direction; and reinforcing ribs each of which extends from an outer peripheral surface portion of the inner ring corresponding to the lip portion to the support leg, and integrally connects the outer peripheral surface of the inner ring, the inner peripheral surface of the outer ring, and the support leg.
    Type: Grant
    Filed: December 20, 1995
    Date of Patent: September 23, 1997
    Assignee: Oiles Corporation
    Inventors: Yoshikazu Sakairi, Atsushi Ueno
  • Patent number: 5476326
    Abstract: A synthetic resin bearing comprised of synthetic resin-made upper and lower bearing cases and a synthetic resin-made bearing member having a disk-shaped thrust bearing piece and a hollow-cylindrical radial bearing piece with a radially extending slit. The bearing member is disposed such that the radial bearing piece is kept in sliding contact with an outer peripheral surface of a hollow cylindrical portion of the lower bearing case, and the thrust bearing piece is kept in sliding contact with a bottom of an annular recess formed in the lower bearing case. The upper bearing case is assembled to the lower bearing case such that an annular engaging hook portion is snappingly fitted over an annular engaging projecting portion of the lower bearing case.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: December 19, 1995
    Assignee: Oiles Corporation
    Inventors: Atsushi Ueno, Tetsuya Aida, Kazuo Kato
  • Patent number: 5352059
    Abstract: A synthetic resin connecting rod is disclosed having a ball socket integrally formed with an opening on one side and a concave spherical surface extending from the opening at each end of the rod. In order to increase the strength, the connecting rod has a rib as a reinforcement on the connecting line between the centers of each spherical surface, the connecting line intersecting a transverse cross section of the rib. A ball joint using the preferred synthetic resin connecting rod is lighter than one using a metal rod and is strong enough to be used as a ball joint for a stabilizer in an automobile.
    Type: Grant
    Filed: December 16, 1991
    Date of Patent: October 4, 1994
    Assignees: Musashi Seimitsu Kogyo Company Ltd., Oiles Corporation
    Inventors: Atsushi Ueno, Yoshimichi Kamiyama, Tatsuyoshi Tsuji, Toshirou Tanaka
  • Patent number: 5267805
    Abstract: A synthetic with an opening at the top and a concave spherical surface extending from the opening, where a ball head of a ball stud is fixed, has a circular concave step on the outer surface of the housing surround the opening. A metal ring is fixed on the circular step so that the strength of the opening of the synthetic resin housing in a radial inward direction is greatly increased to resist the pull-out load on the ball stud. Warping of the opening is thereby prevented.
    Type: Grant
    Filed: December 16, 1991
    Date of Patent: December 7, 1993
    Assignees: Musashi Seimitsu Kogyo Company Limited, Oiles Corporation
    Inventors: Atsushi Ueno, Tatsuyoshi Tsuji, Masataka Tagami, Kenji Yamada
  • Patent number: 4999713
    Abstract: Disclosed is an improved interlocked zooming apparatus used in a two-barrel type stereo scopic camera. The improved interlocked zooming apparatus includes an adjusting apparatus for adjusting the range of movement of one of the zoom lenses and an automatic image magnification adjusting apparatus for matching the rates of the change in size of images formed by two cameras. Since the sizes of the images in each of the wide-angle end and the telephoto end are first made uniform by the adjusting apparatus before sensing an image, the sizes of the images formed by both the cameras are uniform over the entire zoom region.
    Type: Grant
    Filed: March 3, 1989
    Date of Patent: March 12, 1991
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Atsushi Ueno, Takao Suzuki
  • Patent number: 4996123
    Abstract: An optically oriented photoresist material comprised of an organic polymer and an organic crystal material each having a different refractive index to form an optically oriented layer on a substrate wherein the optical waveguide is formed by an effect of the refractive index difference, and in said waveguide layer thus formed, the spread and scattering of lights are suppressed and very fine mask patterns of said photoresist can be produced.
    Type: Grant
    Filed: February 24, 1989
    Date of Patent: February 26, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Noboru Nomura, Atsushi Ueno, Kazuhiko Hashimoto, Satoshi Kinoshita
  • Patent number: 4757354
    Abstract: A projection optical system for photolithography includes a refraction sub-system and a cata-dioptric sub-system optically connected to each other. The refraction sub-system extends at an object side. The cata-dioptric sub-system extends at an image side. The refraction sub-system is generally composed of refracting members. The cata-dioptric sub-system is generally composed of a phase compensating member, a concave mirror, and a convex mirror. The phase compensating member adjoins the refraction sub-system. At least the concave mirror has a central opening through which light passes. The light forms an image at a rear of the concave mirror.
    Type: Grant
    Filed: April 28, 1987
    Date of Patent: July 12, 1988
    Assignee: Matsushita Electrical Industrial Co., Ltd.
    Inventors: Takeo Sato, Nobuhiro Araki, Koichi Kawata, Noboru Nomura, Atsushi Ueno, Shotaro Yoshida
  • Patent number: 4639768
    Abstract: A video signal superimposing device for superimposing and clearly displaying video signals produced from at least two discrete systems includes an input terminal for inputting a color complex video signal, a separation circuit for separating a first brightness signal and a first chroma signal from the color complex video signal, a first generator for generating a second brightness signal, a first mixer circuit for mixing the second brightness signal and the first brightness signal separated by the separation circuit, a second generator for generating a second chroma signal, a second mixer circuit for mixing the second chroma signal and the first chroma signal separated by the separation circuit, and a third mixer circuit for mixing the mixed brightness signal applied from the first mixer circuit and the mixed chroma signal applied to the second mixer circuit.
    Type: Grant
    Filed: October 1, 1984
    Date of Patent: January 27, 1987
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Atsushi Ueno, Takao Abumi
  • Patent number: 4008372
    Abstract: A TV camera wherein both the lens and its control system are completely enclosed in a casing of the camera to protect them from dust, dirt and damage. Massive control knobs are secured on the side wall of the casing for controlling the focus and the zoom. The iris is cable driven by a linear control mounted on the side wall of the casing and the indication of the iris setting is provided on the rear control panel having a viewfinder. A self-balancing cradle mount supports the camera slightly above its center of gravity. Independent pan and tilt friction adjustments can lock the camera in any desired position. A pan and tilt handle is located at the rear of the control panel.
    Type: Grant
    Filed: December 1, 1975
    Date of Patent: February 15, 1977
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Atsushi Ueno, Kiyoharu Sakai, Showhey Fujimoto