Patents by Inventor Atsushi Wada

Atsushi Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7956800
    Abstract: A mobile communication terminal 10A, in a process of acquiring assistance information in advance for using for a GPS position measuring at step S10, makes a judgment of whether or not the assistance information is to be acquired, prior to the GPS position measuring command by a user. When a result of this judgment is affirmative, the terminal 10A transmits an assistance information request to a position measuring assistance server 50. When the assistance information is returned from the position measuring assistance server 50 in response to this the assistance information request, in the cellular phone 10A, the assistance information is received and stored, and then prepared for a command for position measuring by the user, for which possibility of being made is higher in a short period. As a result, it is possible to perform quickly the position measuring of a current location of the mobile communication terminal.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: June 7, 2011
    Assignee: Vodafone Group PLC
    Inventors: Masanori Fujiwara, Satoshi Miyata, Seiichi Kawakami, Jun Sakamoto, Kazuya Kawakami, Atsushi Wada
  • Publication number: 20110076716
    Abstract: A bacteria analysis apparatus comprising: a specimen preparation section for preparing a first measurement specimen from a sample by using a first enzyme; a detecting section for detecting bacteria included in the first measurement specimen; and an information processing section for outputting information for supporting determination of kind of bacteria included in the sample on the basis of the detection result of the first measurement specimen. A method and a computer program product is also disclosed.
    Type: Application
    Filed: September 27, 2010
    Publication date: March 31, 2011
    Applicant: SYSMEX CORPORATION
    Inventor: Atsushi WADA
  • Patent number: 7916199
    Abstract: A pixel includes a photodiode, an overflow circuit, a first sensing circuit, and a second sensing circuit. The first sensing circuit charges and discharges a cathode capacitance by a photocurrent flowing through a photodiode, and amplifies an obtained voltage by a source follower amplifier so as to be outputted to a data line. The second sensing circuit charges and discharged the cathode capacitance by the photocurrent flowing through the photodiode, and outputs electric charge stored in the cathode capacitance via the data line. A pixel circuit is configured so that a first mode in which the first sensing circuit becomes active and a second mode in which the second sensing circuit becomes active can be switched. The first mode and the second mode are switched according to an amount of light received by the photodiode included in each pixel circuit. Gain is controlled according to the amount of light received, in the first mode, and the storage time is controlled in the second mode.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: March 29, 2011
    Assignees: National University Corporation Nara, Institute of Science and Technology Sanyo Electric Co., Ltd.
    Inventors: Keiichiro Kagawa, Jun Ohta, Yugo Nose, Atsushi Wada, Hajime Takashima
  • Publication number: 20100328119
    Abstract: A capacitor array circuit receives a plurality of input signals, generate a single output signal by combining the plurality of input signals, and output the single output signal. A comparator receives the output signal of the capacitor array circuit. A current source, which is disposed between a predetermined fixed voltage source and an output terminal of the switched-capacitor circuit, supplies the current to the output terminal until the output signal of the comparator changes. A plurality of input capacitors in the capacitor array circuit receives a plurality of input signals in parallel with each other. At least one additional regulating capacitor in the capacitor array circuit store the charge to compensate for an offset component caused by the delay in the comparator. The respective output terminals of the plurality of input capacitors and the at least one additional regulating capacitor are combined into one.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 30, 2010
    Inventors: Shigeto Kobayashi, Atsushi Wada, Toru Dan
  • Publication number: 20100253577
    Abstract: A mobile communication terminal 10A, in a process of acquiring assistance information in advance for using for a GPS position measuring at step S10, makes a judgment of whether or not the assistance information is to be acquired, prior to the GPS position measuring command by a user. When a result of this judgment is affirmative, the terminal 10A transmits an assistance information request to a position measuring assistance server 50. When the assistance information is returned from the position measuring assistance server 50 in response to this the assistance information request, in the cellular phone 10A, the assistance information is received and stored, and then prepared for a command for position measuring by the user, for which possibility of being made is higher in a short period. As a result, it is possible to perform quickly the position measuring of a current location of the mobile communication terminal.
    Type: Application
    Filed: January 10, 2007
    Publication date: October 7, 2010
    Applicant: VODAFONE K.K.
    Inventors: Masanori Fujiwara, Satoshi Miyata, Seiichi Kawakami, Jun Sakamoto, Kazuya Kawakami, Atsushi Wada
  • Patent number: 7786775
    Abstract: The object is to provide a delay circuit capable of improving the accuracy of delay time with a simple circuit configuration. A delay circuit includes a first delay unit including a plurality of delay elements connected in series for detecting delay time characteristics of the first delay unit, a detection unit detects the number of delay elements used in the first delay unit to delay an input signal by a reference time, a second delay unit including a plurality of delay elements connected in series so as to output a signal delayed in accordance with the delay time characteristics of the first delay unit, and a selection unit selects the number of delay elements in the second delay unit to delay the input signal in accordance with the number of delay elements detected by the detection unit.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: August 31, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takeshi Otsuka, Atsushi Wada
  • Patent number: 7782176
    Abstract: A mobile information apparatus 10 acquires the display information which is stored in the display area 72, which is secured for using at the time of displaying on the display section by the mobile information apparatus 10, in the storage section 34 of the contactless communication device 30. In this case, in the display area 72, display information which can improve convenience for a user is stored. The display information which is stored includes information such as a result of editing a content of communication performed by the contactless communication, a function performed by the contactless communication by the contactless communication device 30, and an issuer of such function. Then, based on the display information which is acquired, the information of the contactless communication device 30 is displayed on the display section.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: August 24, 2010
    Assignee: Vodafone Group PLC
    Inventors: Yukihiro Mitani, Atsushi Wada, Akinori Ohno, Hideki Nagayanagi, Shoji Kezuka
  • Patent number: 7764214
    Abstract: A sub-A-D converter circuit converts a sampled analog signal into a digital signal of a predetermined number of bits. a D-A converter circuit converts the digital signal converted by the sub-A-D converter circuit into an analog signal to generate a residual signal to be processed by a subsequent conversion processing where the analog signal is to be removed from an analog signal to be sampled by the sub-A-D converter circuit. The D-A converter circuit is of a capacitor array type, and an offset compensation voltage used to compensate for at least part of an offset voltage added to the analog signal sampled by the sub-A-D converter circuit is supplied to at least one capacitor in the capacitor array.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: July 27, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeto Kobayashi, Atsushi Wada
  • Patent number: 7745776
    Abstract: In a photo detecting apparatus, a first capacitance is caused by a photo detecting element and the first capacitance is charged or discharged by current flowing through the photo detecting element. A second capacitance is connected in parallel with the photo detecting element, and the second capacitance charges or discharges an electric charge overflowing from the first capacitance. A current control element is connected to a terminal of the second capacitance on a side where the electric charge flows in, and the current control element delivers a current to cancel part of an electric charge when the electric charge overflowing from the first capacitance is stored in the second capacitance.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: June 29, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Atsushi Wada, Kuniyuki Tani, Hajime Takashima
  • Patent number: 7746138
    Abstract: A plurality of flip-flop circuits, having different circuit configurations, which perform an identical digital signal processing are mixed on a single semiconductor substrate. A first flip-flop circuit among the plurality of flip-flop circuits receives a clock signal supplied from outside the flip-flop circuits, through at least two stage inverters, and operates with clock signals outputted from the inverters. A second flip-flop circuit receives the clock signal supplied from outside the flip-flop circuits through at least one inverter having a less number of stages than the number of stages of the inverter contained in the first flip-flop circuit, and operates with at least one of the clock signal and a clock signal outputted from the inverter.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: June 29, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Satoru Sekine, Yoshitaka Ueda, Takashi Asano, Shinji Furuichi, Atsushi Wada
  • Publication number: 20100080979
    Abstract: [Problems] To provide: a polypropylene resin composition which can produce an expansion-molded article showing excellent low-temperature impact properties even when expanded at an increased expansion rate; an expansion-molded article using the polypropylene resin composition, which has excellent low-temperature impact properties, is light in weight, and has good appearance; and a process for producing the expansion-molded article. [Solution] Using a polypropylene resin composition comprising 100 weight of a polypropylene resin and 1 to 4 parts by weight of a polyethylene wax having a viscosity average molecular weight of 2400 to 3400, an expansion-molded article which is expanded at an expansion rate of 1.5 to 3 times is produced by injection expansion molding by means of a gas counter pressure technique.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 1, 2010
    Inventors: Yasuji Kanamitsu, Kiminori Sato, Satoru Tominaga, Atsushi Wada, Hiroyuki Hirano
  • Patent number: 7667535
    Abstract: Sampling capacitors are connected respectively to a pair of differential input terminals of an operational amplifier. The sampling capacitors sample input signals. Source terminals and drain terminals of dummy switches are connected respectively to paths connecting the operational amplifier and the sampling capacitors, so that a common-mode voltage of differential input voltages to the operational amplifier is adjusted by gate-channel capacitances.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: February 23, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeto Kobayashi, Atsushi Wada
  • Publication number: 20100000209
    Abstract: A hydraulic control system in a working machine includes hydraulic cylinders that make a working part ascend and descend; a first main pump that suctions oil from an oil tank and discharges the oil; an accumulator that accumulates oil discharged from weight holding side oil chambers of the hydraulic cylinders when the working part descends; and a hybrid pump that suctions accumulated oil pressure in the accumulator and discharges the oil pressure. When the working part ascends, discharged oil from the hybrid pump is supplied to the weight holding side oil chambers of the hydraulic cylinders. When an insufficient supply flow from the hybrid pump to the hydraulic cylinders exists, a complementary flow corresponding to the insufficient supply flow is supplied from the first main pump to the weight holding side oil chambers of the hydraulic cylinders.
    Type: Application
    Filed: April 2, 2007
    Publication date: January 7, 2010
    Inventors: Atsushi Wada, Naoyuki Moriya, John R. Gay, Katsuharu Gonmori
  • Patent number: 7556254
    Abstract: A first signal line is provided for transmitting to each of a plurality of paper feeders an output signal from a printing paper sensor provided in the uppermost paper feeder among the plurality thereof. In response to an output signal that has been transmitted via the first signal line, a halting unit causes a halt to processing that is for transporting printing paper in each of the paper feeders.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: July 7, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventor: Atsushi Wada
  • Patent number: 7525383
    Abstract: Connected to a differential transistor pair are a load current source and a tail current source. A bias circuit controls current generated by the load current source. A first self-bias switch is provided between a gate and a drain of a first input transistor; and a second self-bias switch is provided between a gate and a drain of a second input transistor, where the first input transistor and the second input transistor constitute the differential transistors pair. An external bias switch is provided between the bias circuit and the load current source.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: April 28, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeto Kobayashi, Atsushi Wada
  • Publication number: 20090086071
    Abstract: A pixel includes a photodiode, an overflow circuit, a first sensing circuit, and a second sensing circuit. The first sensing circuit charges and discharges a cathode capacitance by a photocurrent flowing through a photodiode, and amplifies an obtained voltage by a source follower amplifier so as to be outputted to a data line. The second sensing circuit charges and discharged the cathode capacitance by the photocurrent flowing through the photodiode, and outputs electric charge stored in the cathode capacitance via the data line. A pixel circuit is configured so that a first mode in which the first sensing circuit becomes active and a second mode in which the second sensing circuit becomes active can be switched. The first mode and the second mode are switched according to an amount of light received by the photodiode included in each pixel circuit. Gain is controlled according to the amount of light received, in the first mode, and the storage time is controlled in the second mode.
    Type: Application
    Filed: January 31, 2007
    Publication date: April 2, 2009
    Inventors: Keiichiro Kagawa, Jun Ohta, Yugo Nose, Atsushi Wada, Hajime Takashima
  • Patent number: 7493385
    Abstract: A maker of a measuring device provides, on a client support system, a WWW server for providing the operation manual of the measuring device in an HTML format, and an ordered article control server for performing a supply control on the expendables of a measuring device. The measuring device has a browsing function, and a monitor unit monitors the status of a control unit to display a proper page in the operation manual on a monitor by requesting a transfer of a URL to the WWW server (24) according to the status of the control unit at that time. Ordering of expendables is possible by means of an ordering screen incorporated in the operation manual.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: February 17, 2009
    Assignee: ARKRAY, Inc.
    Inventor: Atsushi Wada
  • Publication number: 20090033534
    Abstract: A sub-A-D converter circuit converts a sampled analog signal into a digital signal of a predetermined number of bits. a D-A converter circuit converts the digital signal converted by the sub-A-D converter circuit into an analog signal to generate a residual signal to be processed by a subsequent conversion processing where the analog signal is to be removed from an analog signal to be sampled by the sub-A-D converter circuit. The D-A converter circuit is of a capacitor array type, and an offset compensation voltage used to compensate for at least part of an offset voltage added to the analog signal sampled by the sub-A-D converter circuit is supplied to at least one capacitor in the capacitor array.
    Type: Application
    Filed: July 31, 2008
    Publication date: February 5, 2009
    Inventors: Shigeto Kobayashi, Atsushi Wada
  • Publication number: 20080317574
    Abstract: The invention provides a swing drive device that is capable of energy conservation by limiting loss of hydraulic fluid pressure energy resulting from discharge of the hydraulic fluid pressure energy as thermal energy into the air during acceleration or deceleration of swinging action and transforming motion energy to electric energy during deceleration of swinging action, and also enables cost reduction by making components and parts compact.
    Type: Application
    Filed: March 2, 2006
    Publication date: December 25, 2008
    Applicant: SHIN CATERPILLAR MITSUBISHI LTD.
    Inventors: Naoyuki Moriya, Atsushi Wada, Madoka Binnaka
  • Patent number: RE40552
    Abstract: Apparatus and methods for controlling the sensing of bit lines which facilitates the distribution of bit line charging current to be distributed any time, and facilitates the fast raising of the sense modes to full logic levels. An embodiment is comprised of a plurality of bit storage capacitors, a folded bit line for receiving charge stored on one of the capacitors, having bit line capacitance, a sense amplifier having a pair of sense nodes for sensing a voltage differential across the sense nodes, apparatus connected to the bit line and the sense nodes for imperfectly isolating the sense nodes from the bit line whereby current can leak therethrough, apparatus for enabling the sense amplifier and for disabling the isolating apparatus and thereby removing the isolation between the sense amplifier and the bit line, whereby current passing through the sense amplifier to the sense nodes is enabled to charge the bit line capacitance through the isolating apparatus to predetermined logic voltage level.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: October 28, 2008
    Assignee: Mosaid Technologies, Inc.
    Inventors: Richard C. Foss, Peter B. Gillingham, Robert Harland, Masami Mitsuhashi, Atsushi Wada