Abstract: The present invention provides for debugging a target program with a computer comprising a storage unit and a processing unit. In one aspect, this comprises: storing, in the storage unit, reliability information including the reliability of individual indices of classification items of the program; reading, by the processing unit, the reliability information of the target program from the storage unit and determining a reliable code area and an unreliable code area by using the reliability of the individual indices in the reliability information; and executing debugging of the debug target program only for the unreliable code area while omitting debugging of the reliable code area. A graphical user interface to support debugging of only unreliable code areas is also disclosed.

Abstract: A method for efficiently developing software and supporting creation of source code so as to develop software that meets the requirements. A plurality of test cases defining a plurality of respective tests to be executed to check the conformity of the software to the requirements are used. In a test execution step, one or more specific test cases selected from the plurality of test cases are executed or the specific test cases are caused to be executed. Furthermore, a test result of a test case executed or caused to be executed in the test case execution step is added to the source code.

Abstract: A method, system and computer program product for efficiently developing software and supporting creation of source code so as to develop software that meets the requirements. A plurality of test cases defining a plurality of respective tests to be executed to check the conformity of the software to the requirements are used. In a test execution step, one or more specific test cases selected from the plurality of test cases are executed or the specific test cases are caused to be executed. Furthermore, a test result of a test case executed or caused to be executed in the test case execution step is added to the source code.

Abstract: A nonvolatile storage device having a memory cell array composed of a plurality of memory cells. The plurality of memory cells include a bit line to which the drain terminals of the plurality of memory cells that have noncovalent connected gate terminals are commonly connected and a source line to which the source terminals of the plurality of memory cells that have commonly connected gate terminals are commonly connected and which extend perpendicularly to the bit line. The memory cell also includes a first source selector switch for connecting the source line to a source bias line.

Abstract: A nonvolatile memory device is disclosed. The nonvolatile memory device includes a source selector transistor connected at one end thereof to a source line, a plurality of cell selector transistors connected in series with each other and to the other end of said source selector transistor and a basic memory unit including a variable resistor element which is constituted as a memory element to store bit information and is provided for each of said cell selector transistors, being connected at one end thereof to the drain terminal of said cell selector transistor and connected at the other end thereof to the bit line. The source selector transistor and said cell selector transistor provided between one end of said variable resistor element to be accessed and said source line are controlled to turn on.

Abstract: A nonvolatile storage device having a memory cell array composed of a plurality of memory cells. The plurality of memory cells include a bit line to which the drain terminals of the plurality of memory cells that have noncovalent connected gate terminals are commonly connected and a source line to which the source terminals of the plurality of memory cells that have commonly connected gate terminals are commonly connected and which extend perpendicularly to the bit line. The memory cell also includes a first source selector switch for connecting the source line to a source bias line.

Abstract: A nonvolatile memory device is disclosed. The nonvolatile memory device includes a source selector transistor connected at one end thereof to a source line, a plurality of cell selector transistors connected in series with each other and to the other end of said source selector transistor and a basic memory unit including a variable resistor element which is constituted as a memory element to store bit information and is provided for each of said cell selector transistors, being connected at one end thereof to the drain terminal of said cell selector transistor and connected at the other end thereof to the bit line. The source selector transistor and said cell selector transistor provided between one end of said variable resistor element to be accessed and said source line are controlled to turn on.

Abstract: On a channel region enclosed by a pair of diffusion layers 13A, 13B, a first insulating layer 15, a charge accumulative layer 17, and a second insulating layer 19 are stacked up in this order, and on the second insulating layer 19, two control gate layers 21A, 21B spaced across a gap G1 are disposed in the middle of the channel width direction. The charge accumulative layer 17 has discrete charge traps, and, accordingly, movement of charge in the layer is limited. In the charge accumulative layer 17, the charges injected depend on the writing voltage applied in control gate layers 21A, 21B and can be localized beneath the control gate layers 21A, 21B through which a writing voltage is applied. The presence or absence of charges can be controlled in every charge accumulative region beneath the control gate layers 21A, 21B, so that multi-value storage in the memory cell can be realized.

Abstract: On a channel region enclosed by a pair of diffusion layers 13A, 13B, a first insulating layer 15, a charge accumulative layer 17, and a second insulating layer 19 are stacked up in this order, and on the second insulating layer 19, two control gate layers 21A, 21B spaced across a gap G1 are disposed in the middle of the channel width direction. The charge accumulative layer 17 has discrete charge traps, and, accordingly, movement of charge in the layer is limited. In the charge accumulative layer 17, the charges injected depend on the writing voltage applied in control gate layers 21A, 21B and can be localized beneath the control gate layers 21A, 21B through which a writing voltage is applied. The presence or absence of charges can be controlled in every charge accumulative region beneath the control gate layers 21A, 21B, so that multi-value storage in the memory cell can be realized.

Abstract: Disclosed is a method of designing a semiconductor device including a plurality of elements, using a computer-aided design (CAD) apparatus. Data about the basic design of each cell is stored as a cell in a library of the CAD apparatus. In each cell, a plurality of connecting terminal regions for connecting an associated element to an external interconnection are provided as electrically disconnected from an internal circuit forming area of this element. This cell is laid at a desired position in a semiconductor device that is being designed. After the necessary cells are laid out, one of the connecting terminals is selected for each cell from a plurality of connecting terminal regions. Then, an interconnection for connecting the internal circuit forming area to the selected connecting terminal region is designed.