Abstract: A vehicle energy management device includes: an energy consumption related information acquisition unit which acquires energy consumption related information that is information related to energy consumption of an own vehicle in each of traveling sections; an energy consumption related information correction unit which corrects the energy consumption related information; and a control plan production unit which produces a control plan for vehicle instruments based on an estimated value of an energy consumption amount of each of the vehicle instruments calculated by using the corrected energy consumption related information. The energy consumption related information correction unit corrects the energy consumption related information based on a result of comparing an actually measured value of traveling characteristics of the own vehicle in each of the road categories and a statistical result of traveling characteristics of a plurality of general vehicles in each of the traveling sections.

Abstract: Two paths (arrival and required paths) as a target of analysis are united into a single path, and an on-chip random variation component ?r about a plurality of nodes of the single path is calculated. Next, an on-chip variation component ?chip is calculated on the basis of the on-chip random variation component ?r and an on-chip systematic variation component ?s. Subsequently, a delay variation Docv is calculated on the basis of a reference delay Dbase of the entire path and the on-chip variation component ?chip.

Abstract: Two paths (arrival and required paths) as a target of analysis are united into a single path, and an on-chip random variation component ?r about a plurality of nodes of the single path is calculated. Next, an on-chip variation component chip is calculated on the basis of the on-chip random variation component ?r and an on-chip systematic variation component ?s. Subsequently, a delay variation Docv is calculated on the basis of a reference delay Dbase of the entire path and the on-chip variation component ?chip.

Abstract: Two paths (arrival and required paths) as a target of analysis are united into a single path, and an on-chip random variation component ?r about a plurality of nodes of the single path is calculated. Next, an on-chip variation component ?chip is calculated on the basis of the on-chip random variation component ?r and an on-chip systematic variation component ?s. Subsequently, a delay variation Docv is calculated on the basis of a reference delay Dbase of the entire path and the on-chip variation component ?chip.

Abstract: In a pressure increase control valve, the size of a gap G between a plunger and a guide is 0.2 mm or greater, or a ratio between a diameter of a restriction and a seat diameter ds is 0.9 or less. Setting the size of the gap between the plunger and the guide to 0.2 mm or greater can decrease variations in an electromagnetic force with respect to a stroke of a valve body. In addition, setting the ratio between the diameter do of the restriction and the seat diameter to 0.9 or less can increase variations in a fluid force with respect to the stroke of the valve body. Therefore, it is easier to achieve a relationship between the electromagnetic force and a resistance force that is required in order to enable linear control of a differential pressure amount generated between upstream and downstream flows.

Abstract: Two paths (arrival and required paths) as a target of analysis are united into a single path, and an on-chip random variation component ?r about a plurality of nodes of the single path is calculated. Next, an on-chip variation component ?chip is calculated on the basis of the on-chip random variation component ?r and an on-chip systematic variation component ?s. Subsequently, a delay variation Docv is calculated on the basis of a reference delay Dbase of the entire path and the on-chip variation component ?chip.

Abstract: In a pressure increase control valve, the size of a gap G between a plunger and a guide is 0.2 mm or greater, or a ratio between a diameter of a restriction and a seat diameter ds is 0.9 or less. Setting the size of the gap between the plunger and the guide to 0.2 mm or greater can decrease variations in an electromagnetic force with respect to a stroke of a valve body. In addition, setting the ratio between the diameter do of the restriction and the seat diameter to 0.9 or less can increase variations in a fluid force with respect to the stroke of the valve body. Therefore, it is easier to achieve a relationship between the electromagnetic force and a resistance force that is required in order to enable linear control of a differential pressure amount generated between upstream and downstream flows.

Abstract: The present invention provides for adjusting the delay time interval of an input signal by controlling the internal register value and internal signal in a semiconductor integrated circuit device, or an external signal. The invention comprises a first gate array 10 for carrying out fine adjustment of the delay time interval of the input signal, capacitances 60 to 63 and 70 to 73 connected to the output side of a specified gate in the first gate array via first switching device 40 to 43, a second gate array 20 for carrying out rough adjustment of the delay time interval of the input signal; and a control device 30 that adjusts the delay time interval of the input signal by adjusting the capacitances connected to the output side of a specified gate in the first gate array and the number of gate stages in the second gate array 20.

Abstract: A semiconductor integrated circuit including a clock signal propagation gate capable of reducing clock signal skew and controlling a clock signal is provided. The clock signal inputted at a clock origin propagates through buffers (30, 31) to a clock propagation control gate (32). The two-level clock propagation control gate (32) includes an inverter at the first level, and a NAND gate at the second level. The clock signal passed through the clock propagation control gate (32) propagates through buffers (33, 34) to reach a sequential circuit (35) at an end point. The NAND gate (39) at the second level of the clock propagation control gate (32) includes nMOS transistors (42, 43) and pMOS transistors (40, 41). The inverter (36) at the first level includes a pMOS transistor (37) and an nMOS transistor (38).

Abstract: Logic circuits are arranged to constitute a pipeline with a clock signal cycle period set longer than a target cycle period by a gain obtained when replacing a flip-flop circuit by latch circuits. Then, the clock signal cycle period is changed to the target cycle period, to detect a critical path, on which a setup condition error occurs in the pipeline. After replacing the flip-flop circuit related to this error path by complementarily operating latch circuits, related logic circuits are rearranged according to the replacing latch circuits, to meet various operating parameters. In this way, it becomes possible to readily design a pipeline that accurately operates synchronously with a high-speed clock signal.

Abstract: A semiconductor integrated circuit including a clock signal propagation gate capable of reducing clock signal skew and controlling a clock signal is provided. The clock signal inputted at a clock origin propagates through buffers (30, 31) to a clock propagation control gate (32). The two-level clock propagation control gate (32) includes an inverter at the first level, and a NAND gate at the second level. The clock signal passed through the clock propagation control gate (32) propagates through buffers (33, 34) to reach a sequential circuit (35) at an end point. The NAND gate (39) at the second level of the clock propagation control gate (32) includes nMOS transistors (42, 43) and pMOS transistors (40, 41). The inverter (36) at the first level includes a pMOS transistor (37) and an nMOS transistor (38).

Abstract: Logic circuits are arranged to constitute a pipeline with a clock signal cycle period set longer than a target cycle period by a gain obtained when replacing a flip-flop circuit by latch circuits. Then, the clock signal cycle period is changed to the target cycle period, to detect a critical path, on which a setup condition error occurs in the pipeline. After replacing the flip-flop circuit related to this error path by complementarily operating latch circuits, related logic circuits are rearranged according to the replacing latch circuits, to meet various operating parameters. In this way, it becomes possible to readily design a pipeline that accurately operates synchronously with a high-speed clock signal.

Abstract: The present invention provides a multistage pipeline latch circuit that tolerates the displacement of a clock edge by exploiting the insertion positions of the latch circuits and the clock input timing to the latch circuits. A latch circuit, operating as a two or more stage pipeline, provides an input flip flop circuit to which an input signal is applied, an output flip flop circuit that supplies an output signal, and a latch circuit provided between the input and output flip flop circuits, a clock signal supply means that supplies a common clock signal to the input and output flip flop circuits and the latch circuits, and a circuit insertion position selection means that determines the insertion position of the input and output flip flop circuits and the latch circuits so that the input of the latch circuit is defined at the center of the through period of the latch circuits are provided.

Abstract: In an adder apparatus, a first logic circuit performs a NOR operation upon a first bit of an n-bit input signal and a control signal to generate a first signal. A second logic circuit performs an OR operation upon the first bit of the n-bit input signal and the control signal to generate a logic OR signal and performs a NAND operation upon the logic OR signal and a second bit of the n-bit input signal to generate a second signal. Each of third logic circuits performs a NAND operation upon an (i−1)th (i=3, 4, . . . , n) bit of the n-bit input signal and i-th bit of the n-bit input signal to generate a third signal. A carry signal generating circuit receives the first, second and third signals to generate “n” carry signals.

Abstract: The present invention is directed to an electromagnetic valve which includes a cylindrical fixed core, a spring which is mounted at a predetermined position within a hollow portion of the fixed core, a non-magnetic portion which is formed in the fixed core near the spring, and a valve seat member which is disposed at a position away from the predetermined position by a certain distance along a longitudinal axis of the fixed core. And, a movable core is disposed within the hollow portion of the fixed core between the valve seat member and the spring to be movable along the longitudinal axis of the fixed core. The movable core is provided with a stepped columnar portion having a small diameter section formed at its one end portion near the spring, and a large diameter section formed at its the other one end portion near the valve seat member, with a step formed at a boundary between the large diameter section and the small diameter section.

Abstract: The present invention provides for adjusting the delay time interval of an input signal by controlling the internal register value and internal signal in a semiconductor integrated circuit device, or an external signal. The invention comprises a first gate array 10 for carrying out fine adjustment of the delay time interval of the input signal, capacitances 60 to 63 and 70 to 73 connected to the output side of a specified gate in the first gate array via first switching device 40 to 43, a second gate array 20 for carrying out rough adjustment of the delay time interval of the input signal; and a control device 30 that adjusts the delay time interval of the input signal by adjusting the capacitances connected to the output side of a specified gate in the first gate array and the number of gate stages in the second gate array 20.