Patents by Inventor Atsusi Nozoe

Atsusi Nozoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sealed stacked arrangement of semiconductor devices
    Patent number: 5701031
    Abstract: A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
    Type: Grant
    Filed: July 25, 1994
    Date of Patent: December 23, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Oguchi, Masamichi Ishihara, Kazuya Ito, Gen Murakami, Ichiro Anjoh, Toshiyuki Sakuta, Yasunori Yamaguchi, Yasuhiro Kasama, Tetsu Udagawa, Eiji Miyamoto, Youichi Matsuno, Hiroshi Satoh, Atsusi Nozoe
  • Multi-chip semiconductor package
    Patent number: 5332922
    Abstract: A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Each chip is bonded with an associated lead frame and each lead frame is disposed as plural lead frame conductors contacting mutually lead frame conductors associated with similarly function bonding pads, i.e. external terminals of the chips, of the other one of the pair of chips. Ones or plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal.
    Type: Grant
    Filed: April 26, 1991
    Date of Patent: July 26, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Oguchi, Masamichi Ishihara, Kazuya Ito, Gen Murakami, Ichiro Anjoh, Toshiyuki Sakuta, Yasunori Yamaguchi, Yasuhiro Kasama, Tetsu Udagawa, Eiji Miyamoto, Youichi Matsuno, Hiroshi Satoh, Atsusi Nozoe
  • Sealed stacked arrangement of semiconductor devices
    Patent number: RE37539
    Abstract: A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: February 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Oguchi, Masamichi Ishihara, Kazuya Ito, Gen Murakami, Ichiro Anjoh, Toshiyuki Sakuta, Yasunori Yamaguchi, Yasuhiro Kasama, Tetsu Udagawa, Eiji Momose, Youichi Matsuno, Hiroshi Satoh, Atsusi Nozoe