Abstract: Disclosed here is a delaying detection circuit which is employed for reproducing a digital signal from a received signal and has a constitution in which a present input signal is multiplied with an input signal before one symbol time. The delaying detection circuit according to this invention has a constitution including a plurality of delaying circuits which delays an input signal by respectively different delay times and a synthesis circuit which estimates an input signal before one symbol time based on output signals of these delaying circuits so as not to produce errors in a demodulated data even when one symbol time is not an integer multiple of a period of a carrier wave.

Abstract: A frequency error detecting apparatus for an FSK signal communication system in which data symbols are represented by frequencies displaced from a center frequency, includes a counter for counting the number of each type of data symbol in a received signal over a specific period of time, and a multiplier for multiplying the counted number of symbols by the displacement frequency for each symbol to produce a correction value. A counting unit counts the total number of cycles of the received signal over the specific time period to output a counted number which is proportional to the center frequency of the received signal. The correction value is subtracted from this counted number so that a corrected center frequency may be produced which is then compared with the internal center frequency of the receiver, so that a frequency error may be determined.