Patents by Inventor Atsuya Narai

Atsuya Narai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7528011
    Abstract: In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: May 5, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuji Yano, Atsuya Narai
  • Publication number: 20070232054
    Abstract: In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.
    Type: Application
    Filed: May 29, 2007
    Publication date: October 4, 2007
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yuji Yano, Atsuya Narai
  • Patent number: 7276437
    Abstract: In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: October 2, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuji Yano, Atsuya Narai
  • Publication number: 20050148175
    Abstract: In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.
    Type: Application
    Filed: January 5, 2005
    Publication date: July 7, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yuji Yano, Atsuya Narai
  • Patent number: 6657290
    Abstract: A semiconductor device includes a first semiconductor chip and a second semiconductor chip which are laminated on a substrate, wherein electrode terminals which are provided on each of the semiconductor chips are electrically connected to the substrate by first bonding wires and second bonding wires, and an insulation layer is formed between the second bonding wires and the first semiconductor chip.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: December 2, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuki Fukui, Atsuya Narai
  • Publication number: 20020158325
    Abstract: In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.
    Type: Application
    Filed: June 6, 2002
    Publication date: October 31, 2002
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yuji Yano, Atsuya Narai
  • Publication number: 20020096755
    Abstract: A semiconductor device includes a first semiconductor chip and a second semiconductor chip which are laminated on a substrate, wherein electrode terminals which are provided on each of the semiconductor chips are electrically connected to the substrate by first bonding wires and second bonding wires, and an insulation layer is formed between the second bonding wires and the first semiconductor chip.
    Type: Application
    Filed: January 15, 2002
    Publication date: July 25, 2002
    Inventors: Yasuki Fukui, Atsuya Narai
  • Patent number: 6352879
    Abstract: A first semiconductor chip is produced by affixing a thermo-compression sheet to the back surface of a wafer having a circuit formed on its front surface. The first semiconductor chip is mounted on a circuit board including an insulating substrate and a wiring layer provided on the insulating substrate so that the back surface of the first semiconductor chip faces the circuit board. A second semiconductor chip produced in the same manner as the first semiconductor chip is mounted on the first semiconductor chip with its back surface facing the first semiconductor chip. Each of the first and second semiconductor chips is wire-bonded to the wiring layer with a wire. The first and second semiconductor chips and the wire are sealed with a sealing resin. The wiring layer is connected to external connection terminals through via holes provided in the insulating substrate.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: March 5, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuki Fukui, Yoshiki Sota, Yuji Matsune, Atsuya Narai
  • Patent number: 6229217
    Abstract: A first semiconductor chip is produced by affixing a thermo-compression sheet to the back surface of a wafer having a circuit formed on its front surface. The first semiconductor chip is mounted on a circuit board including an insulating substrate and a wiring layer provided on the insulating substrate so that the back surface of the first semiconductor chip faces the circuit board. A second semiconductor chip produced in the same manner as the first semiconductor chip is mounted on the first semiconductor chip with its back surface facing the first semiconductor chip. Each of the first and second semiconductor chips is wire-bonded to the wiring layer with a wire. The first and second semiconductor chips and the wire are sealed with a sealing resin. The wiring layer is connected to external connection terminals through via holes provided in the insulating substrate.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: May 8, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuki Fukui, Yoshiki Sota, Yuji Matsune, Atsuya Narai
  • Patent number: 6100594
    Abstract: A first semiconductor chip is produced by affixing a thermo-compression sheet to the back surface of a wafer having a circuit formed on its front surface. The first semiconductor chip is mounted on a circuit board including an insulating substrate and a wiring layer provided on the insulating substrate so that the back surface of the first semiconductor chip faces the circuit board. A second semiconductor chip produced in the same manner as the first semiconductor chip is mounted on the first semiconductor chip with its back surface facing the first semiconductor chip. Each of the first and second semiconductor chips is wire-bonded to the wiring layer with a wire. The first and second semiconductor chips and the wire are sealed with a sealing resin. The wiring layer is connected to external connection terminals through via holes provided in the insulating substrate.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: August 8, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuki Fukui, Yoshiki Sota, Yuji Matsune, Atsuya Narai
  • Patent number: RE38806
    Abstract: A first semiconductor chip is produced by affixing a thermo-compression sheet to the back surface of a wafer having a circuit formed on its front surface. The first semiconductor chip is mounted on a circuit board including an insulating substrate and a wiring layer provided on the insulating substrate so that the back surface of the first semiconductor chip faces the circuit board. A second semiconductor chip produced in the same manner as the first semiconductor chip is mounted on the first semiconductor chip with its back surface facing the first semiconductor chip. Each of the first and second semiconductor chips is wire-bonded to the wiring layer with a wire. The first and second semiconductor chips and the wire are sealed with a sealing resin. The wiring layer is connected to external connection terminals through via holes provided in the insulating substrate.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: October 4, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuki Fukui, Yoshiki Sota, Yuji Matsune, Atsuya Narai