Patents by Inventor Atsuya Narai
Atsuya Narai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7528011Abstract: In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.Type: GrantFiled: May 29, 2007Date of Patent: May 5, 2009Assignee: Sharp Kabushiki KaishaInventors: Yuji Yano, Atsuya Narai
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Publication number: 20070232054Abstract: In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.Type: ApplicationFiled: May 29, 2007Publication date: October 4, 2007Applicant: Sharp Kabushiki KaishaInventors: Yuji Yano, Atsuya Narai
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Patent number: 7276437Abstract: In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.Type: GrantFiled: January 5, 2005Date of Patent: October 2, 2007Assignee: Sharp Kabushiki KaishaInventors: Yuji Yano, Atsuya Narai
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Publication number: 20050148175Abstract: In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.Type: ApplicationFiled: January 5, 2005Publication date: July 7, 2005Applicant: Sharp Kabushiki KaishaInventors: Yuji Yano, Atsuya Narai
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Patent number: 6657290Abstract: A semiconductor device includes a first semiconductor chip and a second semiconductor chip which are laminated on a substrate, wherein electrode terminals which are provided on each of the semiconductor chips are electrically connected to the substrate by first bonding wires and second bonding wires, and an insulation layer is formed between the second bonding wires and the first semiconductor chip.Type: GrantFiled: January 15, 2002Date of Patent: December 2, 2003Assignee: Sharp Kabushiki KaishaInventors: Yasuki Fukui, Atsuya Narai
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Publication number: 20020158325Abstract: In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.Type: ApplicationFiled: June 6, 2002Publication date: October 31, 2002Applicant: Sharp Kabushiki KaishaInventors: Yuji Yano, Atsuya Narai
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Publication number: 20020096755Abstract: A semiconductor device includes a first semiconductor chip and a second semiconductor chip which are laminated on a substrate, wherein electrode terminals which are provided on each of the semiconductor chips are electrically connected to the substrate by first bonding wires and second bonding wires, and an insulation layer is formed between the second bonding wires and the first semiconductor chip.Type: ApplicationFiled: January 15, 2002Publication date: July 25, 2002Inventors: Yasuki Fukui, Atsuya Narai
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Patent number: 6352879Abstract: A first semiconductor chip is produced by affixing a thermo-compression sheet to the back surface of a wafer having a circuit formed on its front surface. The first semiconductor chip is mounted on a circuit board including an insulating substrate and a wiring layer provided on the insulating substrate so that the back surface of the first semiconductor chip faces the circuit board. A second semiconductor chip produced in the same manner as the first semiconductor chip is mounted on the first semiconductor chip with its back surface facing the first semiconductor chip. Each of the first and second semiconductor chips is wire-bonded to the wiring layer with a wire. The first and second semiconductor chips and the wire are sealed with a sealing resin. The wiring layer is connected to external connection terminals through via holes provided in the insulating substrate.Type: GrantFiled: June 27, 2000Date of Patent: March 5, 2002Assignee: Sharp Kabushiki KaishaInventors: Yasuki Fukui, Yoshiki Sota, Yuji Matsune, Atsuya Narai
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Patent number: 6229217Abstract: A first semiconductor chip is produced by affixing a thermo-compression sheet to the back surface of a wafer having a circuit formed on its front surface. The first semiconductor chip is mounted on a circuit board including an insulating substrate and a wiring layer provided on the insulating substrate so that the back surface of the first semiconductor chip faces the circuit board. A second semiconductor chip produced in the same manner as the first semiconductor chip is mounted on the first semiconductor chip with its back surface facing the first semiconductor chip. Each of the first and second semiconductor chips is wire-bonded to the wiring layer with a wire. The first and second semiconductor chips and the wire are sealed with a sealing resin. The wiring layer is connected to external connection terminals through via holes provided in the insulating substrate.Type: GrantFiled: June 27, 2000Date of Patent: May 8, 2001Assignee: Sharp Kabushiki KaishaInventors: Yasuki Fukui, Yoshiki Sota, Yuji Matsune, Atsuya Narai
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Patent number: 6100594Abstract: A first semiconductor chip is produced by affixing a thermo-compression sheet to the back surface of a wafer having a circuit formed on its front surface. The first semiconductor chip is mounted on a circuit board including an insulating substrate and a wiring layer provided on the insulating substrate so that the back surface of the first semiconductor chip faces the circuit board. A second semiconductor chip produced in the same manner as the first semiconductor chip is mounted on the first semiconductor chip with its back surface facing the first semiconductor chip. Each of the first and second semiconductor chips is wire-bonded to the wiring layer with a wire. The first and second semiconductor chips and the wire are sealed with a sealing resin. The wiring layer is connected to external connection terminals through via holes provided in the insulating substrate.Type: GrantFiled: December 30, 1998Date of Patent: August 8, 2000Assignee: Sharp Kabushiki KaishaInventors: Yasuki Fukui, Yoshiki Sota, Yuji Matsune, Atsuya Narai
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Patent number: RE38806Abstract: A first semiconductor chip is produced by affixing a thermo-compression sheet to the back surface of a wafer having a circuit formed on its front surface. The first semiconductor chip is mounted on a circuit board including an insulating substrate and a wiring layer provided on the insulating substrate so that the back surface of the first semiconductor chip faces the circuit board. A second semiconductor chip produced in the same manner as the first semiconductor chip is mounted on the first semiconductor chip with its back surface facing the first semiconductor chip. Each of the first and second semiconductor chips is wire-bonded to the wiring layer with a wire. The first and second semiconductor chips and the wire are sealed with a sealing resin. The wiring layer is connected to external connection terminals through via holes provided in the insulating substrate.Type: GrantFiled: May 2, 2003Date of Patent: October 4, 2005Assignee: Sharp Kabushiki KaishaInventors: Yasuki Fukui, Yoshiki Sota, Yuji Matsune, Atsuya Narai