Abstract: This communication system is equipped with a plurality of transceiver devices each composed of a transmission device that transmits unit data and a reception device that receives unit data from the transmission device. The transmission devices are connected in series. Each of the transmission devices stores identification information for identifying the device itself. The transmission device accepts unit data from a front stage side. The transmission device generates identification information for identifying one of the transmission devices from information included in the accepted unit data, in accordance with a predetermined generation process. In a case that the generated identification information corresponds to the stored identification information, the transmission device transmits the accepted unit data to the reception device.

Abstract: A data transfer device 210 is equipped with a plurality of communication ports 211a and 211b, a communication establishment processor 212, and a communication maintenance processor 213. The communication establishment processor 212 transmits and receives communication establishing information for establishing communication with an external device connected via the communication port to and from the external device. The communication maintenance processor 213 is configured to operate independently of the communication establishment processor 212 and, every time a predetermined transmission period elapses, transmits communication maintaining information for maintaining the establishment of communication with the external device, to the external device.

Abstract: A link control function unit 506 of a device 500 notifies a counterpart device 600 of a line in which a link disconnection occurs among lines 508 to 510 and L500 terminated at line terminals 501 to 503 or a lower stage line terminal 504 of the self device 500 and the cause of the link disconnection is not a forcible closure of a line terminal of the self device. Further, the link control function unit 506 does not forcibly close the lower stage line terminal 504 of the self device 500 if a line in which a link disconnection occurs, notified from the counterpart device 600, is a line terminated at a lower stage line terminal 604 of the counterpart device 600.

Abstract: A switching device includes a plurality of input/output ports, a forwarding table that correlates the IP address with the port via which a packet having the IP address as a destination is to be output, and a packet send/receive controller. The packet send/receive controller references the forwarding table to forward a received packet via the port correlated with the destination IP address of the received packet. The packet send/receive controller updates the forwarding table as to a source IP address of the received packet and as to a port that received the packet. A plural number of ports may be correlated with a single IP address in the forwarding table. In case the plural number of the ports are correlated with the single IP address, the packet send/receive controller forwards the received packet via the correlated plural number of the ports.

Abstract: When the synchronization information, transmitted from a synchronization information output unit of a clock master side device, is detected by a synchronization information detection unit, the clock slave side device associates the synchronization information with the timestamp information at the time of detection of the synchronization information. Based on the timestamp information associated with the currently received synchronization information, the timestamp information associated with at least one synchronization information up to the synchronization information received last time and transmission period information of the synchronization information, a calculation/decision unit decides whether or not a predetermined condition is met. When the condition is met, the calculation/decision unit supplies the currently received synchronization information to a clock synchronization technique function unit.

Abstract: A link control function unit 506 of a device 500 notifies a counterpart device 600 of a line in which a link disconnection occurs among lines 508 to 510 and L500 terminated at line terminals 501 to 503 or a lower stage line terminal 504 of the self device 500 and the cause of the link disconnection is not a forcible closure of a line terminal of the self device. Further, the link control function unit 506 does not forcibly close the lower stage line terminal 504 of the self device 500 if a line in which a link disconnection occurs, notified from the counterpart device 600, is a line terminated at a lower stage line terminal 604 of the counterpart device 600.

Abstract: A data transfer device 210 is equipped with a plurality of communication ports 211a and 211b, a communication establishment processor 212, and a communication maintenance processor 213. The communication establishment processor 212 transmits and receives communication establishing information for establishing communication with an external device connected via the communication port to and from the external device. The communication maintenance processor 213 is configured to operate independently of the communication establishment processor 212 and, every time a predetermined transmission period elapses, transmits communication maintaining information for maintaining the establishment of communication with the external device, to the external device.

Abstract: This communication system is equipped with a plurality of transceiver devices each composed of a transmission device that transmits unit data and a reception device that receives unit data from the transmission device. The transmission devices are connected in series. Each of the transmission devices stores identification information for identifying the device itself. The transmission device accepts unit data from a front stage side. The transmission device generates identification information for identifying one of the transmission devices from information included in the accepted unit data, in accordance with a predetermined generation process. In a case that the generated identification information corresponds to the stored identification information, the transmission device transmits the accepted unit data to the reception device.

Abstract: When the synchronization information, transmitted from a synchronization information output unit of a clock master side device, is detected by a synchronization information detection unit, the clock slave side device associates the synchronization information with the timestamp information at the time of detection of the synchronization information. Based on the timestamp information associated with the currently received synchronization information, the timestamp information associated with at least one synchronization information up to the synchronization information received last time and transmission period information of the synchronization information, a calculation/decision unit decides whether or not a predetermined condition is met. When the condition is met, the calculation/decision unit supplies the currently received synchronization information to a clock synchronization technique function unit.

Abstract: A network interconnection system has a plurality of input and output ports that are connected to different networks. An input interface connected to each of the input ports converts the input signal to an LCH packet signal when an input signal is not a MAC frame. A form of the LCH packet signal is identical to the MAC frame and a content of the LCH packet signal corresponding to a source address field of the MAC frame is set to all 0, which is inhibited in the MAC frame format. An output interface connected to each of the output ports converts the LCH packet signal to a signal conforming to a corresponding network when receiving an LCH packet signal as an output signal.

Abstract: An I/F apparatus (D-Ether) with a high-speed/high reliability interface function is provided for a typical network configuration comprising information processing devices such as a plurality of computers (PCs), 100Base-T hubs (HUBs), and 100Base-T Ether cables (Ethers) for connection among them, and a local bus (bus) with a higher speed than that of the Ethers connects a PC to the D-Ether. The D-Ether includes a plurality of LAN controllers and has a function for receiving IP packets at high speed from PC (5) to sequentially transfer the IP packets to the plurality of ports at the speed of the Ether. In addition, the D-Ether has a function for receiving IP packets from the plurality of ports to transfer the IP packets to PC (5) or another Ether port. The transfer processing is performed with reference to a MAC to port table memory in which information on transfer targets of IP packets and ports to be used is stored.

Abstract: A network interconnection system allowing simplified processing of signal conversion is disclosed. The network interconnection system has a plurality of input and output ports that are connected to different networks. An input interface connected to each of the input ports converts the input signal to an LCH packet signal when an input signal is not a MAC frame. A form of the LCH packet signal is identical to the MAC frame and a content of the LCH packet signal corresponding to a source address field of the MAC frame is set to all 0, which is inhibited in the MAC frame format. An output interface connected to each of the output ports converts the LCH packet signal to a signal conforming to a corresponding network when receiving an LCH packet signal as an output signal. A switch forwards an LCH packet signal received from one of input interfaces to an appropriate one of output interfaces based on a destination of an original signal of the received LCH packet signal.

Abstract: A watch dog timer system which has an abnormality checking function of a high degree of reliability. In the watch dog timer system, abnormality of a computer system is detected as a variation of a value allocated in accordance with an execution condition of a program. To this end, a register receives execution state data defined in accordance with an execution condition of the program from a processor or CPU of the computer system and stores the execution state data before a counter of the watch dog timer system overflows. A comparator compares the execution condition data stored in the register and state sequence data indicative of a state sequence of the program stored in a ROM in advance with each other and generates a reset signal for resetting the computer system when the comparison reveals incoincidence.