Abstract: A computer implemented method for designing a semiconductor device, comprising: creating a double cut via including: placing a first line pattern on a chip area, placing a second line pattern on an upper layer of the first line pattern, allocating a first via pattern on an intersection of the first and second line patterns, creating a protrusion line pattern; and allocating a second via pattern on an end of the protrusion line pattern; storing the double cut via; and extracting a single cut via provided on the chip area and replacing the single cut via with the double cut via.

Abstract: A computer implemented method for designing a semiconductor device, comprising: creating a double cut via including: placing a first line pattern on a chip area, placing a second line pattern on an upper layer of the first line pattern, allocating a first via pattern on an intersection of the first and second line patterns, creating a protrusion line pattern; and allocating a second via pattern on an end of the protrusion line pattern; storing the double cut via; and extracting a single cut via provided on the chip area and replacing the single cut via with the double cut via.

Abstract: A semiconductor integrated circuit includes a plurality of first wires running in a first direction of 0°, a 45° diagonal, a 90° angle and a 135° diagonal in a subject area disposed in a designated wiring layer in a multilevel interconnection; and a plurality of second wires running in a second direction of 0°, the 45° diagonal, the 90° angle and the 135° diagonal in a wiring region other than the designated region in the designated wiring layer.