Abstract: Fabricate a panel (5) by building a sacrificial relief (10) by an additive process of multilayer deposition, applying a facade layer (20,30) over the sacrificial relief so as to conform to the contour of the sacrificial relief, depositing a foamable composition (40, 50, 60) over the facade layer.

Abstract: Chalcogenide based photovoltaic devices cells with good resistance to environmental elements can be formed by direct low temperature deposition of inorganic barrier layers onto the film. A unique multilayer barrier can be formed in a single step when reactive sputtering of the silicon nitride onto an inorganic oxide top layer of the PV device.

Abstract: The present invention relates to a power core comprising: at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and at least one planar capacitor laminate; wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate.

Abstract: A solder preform having multiple layers including a solder layer filled with additives interposed between two unfilled layers for improved wettability. A solder preform having a sphere which contains a solder material filled with additives, and an unfilled surface layer for improved wettability. A thermal interface material having a bonding component and an additive component which is a CTE modifying component and/or a thermal conductivity enhancement component. Active solders containing intrinsic oxygen getters.

Abstract: The present invention relates to a device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said at least one embedded singulated capacitor; and wherein said at least one embedded singulated capacitor is connected in parallel to at least one of the said planar capacitor laminates; and wherein said power core is interconnected to at least one signal layer.

Abstract: A solder preform having multiple layers including a solder layer filled with additives interposed between two unfilled layers for improved wettability. A solder preform having a sphere which contains a solder material filled with additives, and an unfilled surface layer for improved wettability. A thermal interface material having a bonding component and an additive component which is a CTE modifying component and/or a thermal conductivity enhancement component. Active solders containing intrinsic oxygen getters.

Abstract: A solder preform having multiple layers including a solder layer filled with additives interposed between two unfilled layers for improved wettability. A solder preform having a sphere which contains a solder material filled with additives, and an unfilled surface layer for improved wettability. A thermal interface material having a bonding component and an additive component which is a CTE modifying component and/or a thermal conductivity enhancement component. Active solders containing intrinsic oxygen getters.

Abstract: A thermal interface material for use in electronic packaging, the thermal interface material comprises a solder with relatively high heat flow characteristics and a CTE modifying component to reduce or prevent damage due to thermal cycling. The thermal interface material comprises an active solder that contains indium and an intrinsic oxygen getter selected from the group consisting of alkali metals, alkaline-earth metals, refractory metals, rare earth metals and zinc and mixtures and alloys thereof. Lastly, damage due to an electronic package due to thermal cycling stress is reduced by using an insert in a lid of an electronic device package wherein the insert has a coefficient of thermal expansion that is between about that of the lid and about that of a semiconductor substrate.