Patents by Inventor Atuk KATOCH

Atuk KATOCH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY DEVICE INCLUDING MEMORY CELLS AND EDGE CELLS
    Publication number: 20240153550
    Abstract: A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Inventor: Atuk KATOCH
  • Memory device including memory cells and edge cells
    Patent number: 11900994
    Abstract: A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Atuk Katoch
  • MEMORY DEVICE INCLUDING MEMORY CELLS AND EDGE CELLS
    Publication number: 20220384453
    Abstract: A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventor: Atuk KATOCH
  • Memory device including memory cells and edge cells
    Patent number: 11488661
    Abstract: A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: November 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Atuk Katoch
  • MEMORY DEVICE INCLUDING MEMORY CELLS AND EDGE CELLS
    Publication number: 20220319584
    Abstract: A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.
    Type: Application
    Filed: April 1, 2021
    Publication date: October 6, 2022
    Inventor: Atuk KATOCH