Patents by Inventor Atul A. Tambe

Atul A. Tambe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11321271
    Abstract: In one embodiment, a method includes initiating cluster parameters that govern how a non-volatile memory (NVM) cluster functions and operates. Submission and completion queues of shared NVM on other nodes in the NVM cluster are mapped based on details of the shared NVM on the other nodes in the NVM cluster. The submission queue is configured to store commands to access the shared NVM according to a first-in-first-out (FIFO) scheme. The completion queue is configured to store completed commands after being processed through the submission queue. In another embodiment, a host-based data storage system includes NVM configured to store data. The host-based data storage system further includes a processor and logic integrated with and/or executable by the processor to perform the foregoing method.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: May 3, 2022
    Assignee: Kyndryl, Inc.
    Inventors: Keshav G. Kamble, Vijoy A. Pandey, Atul A. Tambe
  • Publication number: 20180322088
    Abstract: In one embodiment, a method includes initiating cluster parameters that govern how a non-volatile memory (NVM) cluster functions and operates. Submission and completion queues of shared NVM on other nodes in the NVM cluster are mapped based on details of the shared NVM on the other nodes in the NVM cluster. The submission queue is configured to store commands to access the shared NVM according to a first-in-first-out (FIFO) scheme. The completion queue is configured to store completed commands after being processed through the submission queue. In another embodiment, a host-based data storage system includes NVM configured to store data. The host-based data storage system further includes a processor and logic integrated with and/or executable by the processor to perform the foregoing method.
    Type: Application
    Filed: July 11, 2018
    Publication date: November 8, 2018
    Inventors: Keshav G. Kamble, Vijoy A. Pandey, Atul A. Tambe
  • Patent number: 10061743
    Abstract: In one embodiment, a system includes non-volatile memory (NVM) configured to store data, a memory controller connected to the NVM via a NVM interface, a network interface card (NIC) connected to the memory controller, a processor, the logic being configured to: initiate cluster parameters that govern how a NVM cluster will function and operate, multicast cluster parameters of the NVM cluster at predetermined intervals to any other node in the NVM cluster, and map submission and completion queues of any shared NVM on other nodes in the NVM cluster to the memory controller based on details of the shared NVM on the other nodes in the NVM cluster, wherein the submission queue is configured to store commands to access the shared NVM and the completion queue is configured to store completed commands after being processed through the submission queue.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: August 28, 2018
    Assignee: International Business Machines Corporation
    Inventors: Keshav G. Kamble, Vijoy A. Pandey, Atul A. Tambe
  • Patent number: 9893987
    Abstract: In one embodiment, a method includes sending a switch discovery signal to one or more of a plurality of switches, receiving a reply to the switch discovery signal from the one or more of the plurality of switches, each reply comprising a switch identifier (ID) and a quantity of ports, receiving configuration information identifying at least one virtual stack to create, determining a virtual topology for the at least one virtual stack based on the configuration information, creating a first virtual stack of the at least one virtual stack by assigning at least one switch port of a source switch to the first virtual stack of the at least one virtual stack in accordance with the configuration information, and storing the virtual topology in a mapping table local to a computer comprising the first computer processor.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Keshav G. Kamble, Selvaraj Rajan, Atul A. Tambe
  • Publication number: 20170126555
    Abstract: In one embodiment, a method includes sending a switch discovery signal to one or more of a plurality of switches, receiving a reply to the switch discovery signal from the one or more of the plurality of switches, each reply comprising a switch identifier (ID) and a quantity of ports, receiving configuration information identifying at least one virtual stack to create, determining a virtual topology for the at least one virtual stack based on the configuration information, creating a first virtual stack of the at least one virtual stack by assigning at least one switch port of a source switch to the first virtual stack of the at least one virtual stack in accordance with the configuration information, and storing the virtual topology in a mapping table local to a computer comprising the first computer processor.
    Type: Application
    Filed: January 13, 2017
    Publication date: May 4, 2017
    Inventors: Keshav G. Kamble, Selvaraj Rajan, Atul A. Tambe
  • Patent number: 9602441
    Abstract: A first processor assigns switches and/or switch ports to a virtual stack according to configuration information and stores the virtual topography of the virtual stack in a mapping table. The mapping table correlates switches, switch ports, computer processors, and virtual stacks. The first processor receives a data unit from a first switch that includes a source address and a destination address. The destination address identifies a switch and switch port. The first processor compares the destination address to the mapping table to determine a second computer processor and sends the data unit to the second computer processor, the second computer processor corresponding to a switch and/or switch port identified in the destination address of the data unit.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Keshav G. Kamble, Selvaraj Rajan, Atul A. Tambe
  • Publication number: 20160217104
    Abstract: In one embodiment, a system includes non-volatile memory (NVM) configured to store data, a memory controller connected to the NVM via a NVM interface, a network interface card (NIC) connected to the memory controller, a processor, the logic being configured to: initiate cluster parameters that govern how a NVM cluster will function and operate, multicast cluster parameters of the NVM cluster at predetermined intervals to any other node in the NVM cluster, and map submission and completion queues of any shared NVM on other nodes in the NVM cluster to the memory controller based on details of the shared NVM on the other nodes in the NVM cluster, wherein the submission queue is configured to store commands to access the shared NVM and the completion queue is configured to store completed commands after being processed through the submission queue.
    Type: Application
    Filed: January 27, 2015
    Publication date: July 28, 2016
    Inventors: Keshav G. Kamble, Vijoy A. Pandey, Atul A. Tambe
  • Publication number: 20150085704
    Abstract: A first processor assigns switches and/or switch ports to a virtual stack according to configuration information and stores the virtual topography of the virtual stack in a mapping table. The mapping table correlates switches, switch ports, computer processors, and virtual stacks. The first processor receives a data unit from a first switch that includes a source address and a destination address. The destination address identifies a switch and switch port. The first processor compares the destination address to the mapping table to determine a second computer processor and sends the data unit to the second computer processor, the second computer processor corresponding to a switch and/or switch port identified in the destination address of the data unit.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: Keshav G. Kamble, Selvaraj Rajan, Atul A. Tambe
  • Patent number: 8982905
    Abstract: A system includes scaled-out fabric coupler (SFC) boxes and distributed line card (DLC) boxes. Each SFC box has fabric ports and a cell-based switch fabric for switching cells. Each DLC box is in communication with every SFC box. Each DLC box has network ports receiving packets and network processors. Each processor has a fabric interface that provides SerDes channels. The processors divide each packet received over the network ports into cells and distribute the cells of each packet across the SerDes channels. Each DLC box further comprises DLC fabric ports through which the DLC is in communication with the SFCs. Each DLC fabric port includes a pluggable interface with a given number of lanes over which to transmit and receive cells. Each lane is mapped to one of the SerDes channels such that an equal number of SerDes channels of each fabric interface is mapped to each DLC fabric port.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Keshav Govind Kamble, Alexander Philip Campbell, Atul A. Tambe, Vijoy A. Pandey
  • Publication number: 20120297103
    Abstract: A system includes scaled-out fabric coupler (SFC) boxes and distributed line card (DLC) boxes. Each SFC box has fabric ports and a cell-based switch fabric for switching cells. Each DLC box is in communication with every SFC box. Each DLC box has network ports receiving packets and network processors. Each processor has a fabric interface that provides SerDes channels. The processors divide each packet received over the network ports into cells and distribute the cells of each packet across the SerDes channels. Each DLC box further comprises DLC fabric ports through which the DLC is in communication with the SFCs. Each DLC fabric port includes a pluggable interface with a given number of lanes over which to transmit and receive cells. Each lane is mapped to one of the SerDes channels such that an equal number of SerDes channels of each fabric interface is mapped to each DLC fabric port.
    Type: Application
    Filed: August 31, 2011
    Publication date: November 22, 2012
    Applicant: International Business Machines Corporation
    Inventors: Keshav Govind Kamble, Alexander Philip Campbell, Atul A. Tambe, Vijoy A. Pandey
  • Patent number: 7072546
    Abstract: A plurality of channels of a wavelength division multiplexing system may be subjected to dispersion compensation in a fashion which enables tuning of the compensation for each individual wavelength channel. Moreover, the tuning may be done in a space-efficient fashion. The chirped Bragg gratings may be formed, for example, on a planar light circuit. Each grating may be heated to controllably adjust its dispersion compensation, in one embodiment of the present invention.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: July 4, 2006
    Assignee: Intel Corporation
    Inventors: Dmitri E. Nikonov, Thomas G. Willis, Anders Grunnet-Jepsen, Atul A. Tambe
  • Publication number: 20040184730
    Abstract: A plurality of channels of a wavelength division multiplexing system may be subjected to dispersion compensation in a fashion which enables tuning of the compensation for each individual wavelength channel. Moreover, the tuning may be done in a space-efficient fashion. The chirped Bragg gratings may be formed, for example, on a planar light circuit. Each grating may be heated to controllably adjust its dispersion compensation, in one embodiment of the present invention.
    Type: Application
    Filed: March 21, 2003
    Publication date: September 23, 2004
    Inventors: Dmitri E. Nikonov, Thomas G. Willis, Anders Grunnet-Jepsen, Atul A. Tambe