Patents by Inventor Atul Ajmera
Atul Ajmera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7741165Abstract: A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.Type: GrantFiled: May 12, 2008Date of Patent: June 22, 2010Assignee: International Business Machines CorporationInventors: Kevin Kok Chan, Robert J. Miller, Erin C. Jones, Atul Ajmera
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Publication number: 20080248635Abstract: A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.Type: ApplicationFiled: May 12, 2008Publication date: October 9, 2008Applicant: International Business Machines CorporationInventors: Kevin Kok Chan, Rober J. Miller, Erin C. Jones, Atul Ajmera
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Patent number: 7387924Abstract: A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.Type: GrantFiled: September 18, 2006Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: Kevin Kok Chan, Robert J. Miller, Erin C. Jones, Atul Ajmera
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Publication number: 20070254420Abstract: Methods for source/drain implantation and strain transfer to a channel of a semiconductor device and a related semiconductor device are disclosed. In one embodiment, the method includes using a first size spacer for deep source/drain implantation adjacent a gate region of a semiconductor device; and using a second, smaller size spacer for silicide formation adjacent the gate region and transferring strain from a stress liner to a channel underlying the gate region. One embodiment of a semiconductor device may include a gate region atop a substrate; a spacer including a spacer core and an outer spacer member about the spacer core; a deep source/drain region within the substrate and distanced from the spacer; and a silicide region within the substrate and overlapping and extending beyond the deep source/drain region, the silicide region aligned to the spacer.Type: ApplicationFiled: April 28, 2006Publication date: November 1, 2007Applicants: International Business Machines Corporation, Chartered Semiconductor Manufacturing LTD.Inventors: Atul Ajmera, Christopher Baiocco, Xiangdong Chen, Thomas Dyer, Sunfei Fang, Wenzhi Gao
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Publication number: 20070202654Abstract: Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.Type: ApplicationFiled: February 28, 2006Publication date: August 30, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Atul Ajmera, Christopher Baiocco, Xiangdong Chen, Wenzhi Gao, Young Way Teh
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Publication number: 20070122988Abstract: A method of forming a semiconductor device that embeds an L-shaped spacer is provided. The method includes defining an L-shaped spacer on each side of a gate region of a substrate and embedding the L-shaped spacers in an oxide layer so that the oxide layer extends over a portion of the substrate a predetermined distance from a lateral edge of the L-shaped spacer. And removing oxide layers to expose the L-shape spacers.Type: ApplicationFiled: November 29, 2005Publication date: May 31, 2007Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Zhijiong Luo, Young Teh, Atul Ajmera
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Publication number: 20070010076Abstract: A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.Type: ApplicationFiled: September 18, 2006Publication date: January 11, 2007Applicant: International Business Machines CorporationInventors: Kevin Chan, Rober Miller, Erin Jones, Atul Ajmera
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Patent number: 7135391Abstract: A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.Type: GrantFiled: May 21, 2004Date of Patent: November 14, 2006Assignee: International Business Machines CorporationInventors: Kevin Kok Chan, Rober J. Miller, Erin C. Jones, Atul Ajmera
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Publication number: 20060057797Abstract: A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains.Type: ApplicationFiled: November 4, 2005Publication date: March 16, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Atul Ajmera, Andres Bryant, Percy Gilbert, Michael Gribelyuk, Edward Maciejewski, Renee Mo, Shreesh Narasimha
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Publication number: 20050260832Abstract: A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.Type: ApplicationFiled: May 21, 2004Publication date: November 24, 2005Inventors: Kevin Chan, Rober Miller, Erin Jones, Atul Ajmera
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Publication number: 20050064635Abstract: A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains.Type: ApplicationFiled: September 22, 2003Publication date: March 24, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Atul Ajmera, Andres Bryant, Percy Gilbert, Michael Gribelyuk, Edward Maciejewski, Renee Mo, Shreesh Narasimha
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Patent number: 6521947Abstract: A method for forming a substrate contact in a substrate that includes a silicon on insulator region. A shallow isolation trench is formed in the silicon on insulator substrate. The shallow isolation trench is filled. Photoresist is deposited on the substrate. A contact trench is formed in the substrate through the filled shallow isolation trench, silicon on insulator, and silicon substrate underlying the silicon on insulator region. The contact trench is filled, wherein the material filling the contact trench forms a contact to the silicon substrate.Type: GrantFiled: January 28, 1999Date of Patent: February 18, 2003Assignee: International Business Machines CorporationInventors: Atul Ajmera, Effendi Leobandung, Werner Rausch, Dominic J. Schepis, Ghavam G. Shahidi
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Publication number: 20010041395Abstract: A process for forming a planar silicon-on-insulator (SOI) substrate comprising a patterned SOI region and a bulk region, wherein the substrate is free of transitional defects. The process comprises removing the transitional defects by creating a self-aligned trench adjacent the SOI region between the SOI region and the bulk region.Type: ApplicationFiled: June 5, 2001Publication date: November 15, 2001Inventors: Atul Ajmera, Devendra K. Sadana, Dominic J. Schepis
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Patent number: 6255145Abstract: A process for forming a planar silicon-on-insulator (SOI) substrate comprising a patterned SOI region and a bulk region, wherein the substrate is free of transitional defects. The process comprises removing the transitional defects by creating a self-aligned trench adjacent the SOI region between the SOI region and the bulk region.Type: GrantFiled: January 8, 1999Date of Patent: July 3, 2001Assignee: International Business Machines CorporationInventors: Atul Ajmera, Devendra K. Sadana, Dominic J. Schepis
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Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures
Patent number: 5747866Abstract: Silicon integrated circuits use a crystalline layer of silicon nitride (Si.sub.3 N.sub.4) in shallow trench isolation (STI) structures as an O.sub.2 -barrier film. The crystalline Si.sub.3 N.sub.4 lowers the density of electron traps as compared with as-deposited, amorphous Si.sub.3 N.sub.4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si.sub.3 N.sub.4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si.sub.3 N.sub.4 film is deposited at temperatures of 720.degree. C. to 780.degree. C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050.degree. C. to 1100.degree. for 60 seconds.Type: GrantFiled: January 21, 1997Date of Patent: May 5, 1998Assignee: Siemens AktiengesellschaftInventors: Herbert Ho, Erwin Hammerl, David M. Dobuzinsky, Herbert Palm, Stephen Fugardi, Atul Ajmera, James F. Moseman, Samuel C. Ramac -
Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures
Patent number: 5643823Abstract: Silicon integrated circuits use a crystalline layer of silicon nitride (Si.sub.3 N.sub.4) in shallow trench isolation (STI) structures as an O.sub.2 -barrier film. The crystalline Si.sub.3 N.sub.4 lowers the density of electron traps as compared with as-deposited, amorphous Si.sub.3 N.sub.4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si.sub.3 N.sub.4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si.sub.3 N.sub.4 film is deposited at temperatures of 720.degree. C. to 780.degree. C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050.degree. C. to 1100.degree. C. for 60 seconds.Type: GrantFiled: September 21, 1995Date of Patent: July 1, 1997Assignees: Siemens Aktiengesellschaft, International Business Machines CorporationInventors: Herbert Ho, Erwin Hammerl, David M. Dobuzinsky, J. Herbert Palm, Stephen Fugardi, Atul Ajmera, James F. Moseman, Samuel C. Ramac