Abstract: A system-on-chip (SoC) includes a memory, a trust provisioning system, a one-time programmable (OTP) element, and a comparator. The memory is configured to store a first secret key before an execution of a trust provisioning operation. The trust provisioning system is configured to receive an encrypted version of a first set of secure assets and one of a second secret key and an encrypted version of the second secret key, and execute the trust provisioning operation on the SoC to store the first set of secure assets and the second secret key in the OTP element. The comparator is configured to compare the first and second secret keys to generate a valid signal that is indicative of a validation of the trust provisioning operation. The first set of secure assets and a second set of secure assets associated with the SoC are accessible based on the valid signal.

Abstract: An enabling system that includes a controller and processing circuitry, is configured to enable an external oscillator that operates in one of single-ended, differential, and crystal modes. To enable the external oscillator, the controller is configured to detect a mode of operation of the external oscillator, and the processing circuitry is configured to operate in the detected mode. The controller detects the mode of operation of the external oscillator by sequentially initializing the processing circuitry to operate in the single-ended, differential, and crystal modes, and determining whether the current operating mode of the processing circuitry is same as the mode of operation of the external oscillator based on a clock signal outputted by the processing circuitry during the corresponding mode.

Abstract: A system-on-chip (SoC) includes a memory, a trust provisioning system, a one-time programmable (OTP) element, and a comparator. The memory is configured to store a first secret key before an execution of a trust provisioning operation. The trust provisioning system is configured to receive an encrypted version of a first set of secure assets and one of a second secret key and an encrypted version of the second secret key, and execute the trust provisioning operation on the SoC to store the first set of secure assets and the second secret key in the OTP element. The comparator is configured to compare the first and second secret keys to generate a valid signal that is indicative of a validation of the trust provisioning operation. The first set of secure assets and a second set of secure assets associated with the SoC are accessible based on the valid signal.

Abstract: An enabling system that includes a controller and processing circuitry, is configured to enable an external oscillator that operates in one of single-ended, differential, and crystal modes. To enable the external oscillator, the controller is configured to detect a mode of operation of the external oscillator, and the processing circuitry is configured to operate in the detected mode. The controller detects the mode of operation of the external oscillator by sequentially initializing the processing circuitry to operate in the single-ended, differential, and crystal modes, and determining whether the current operating mode of the processing circuitry is same as the mode of operation of the external oscillator based on a clock signal outputted by the processing circuitry during the corresponding mode.

Abstract: A secure read-only-memory (ROM) code patching system includes a processor that is configured to generate first partial cryptographic data based on a ROM patch and a set of secret bits, and authenticate the ROM patch based on a match between the first partial cryptographic data and reference partial cryptographic data of the ROM patch. Upon the authentication of the ROM patch, the processor is further configured to generate an address associated with a set of ROM instructions of a ROM code. Based on a match between the generated address and a ROM patch address of the ROM patch, the processor is further configured to execute a set of patch instructions of the ROM patch that is successfully authenticated instead of the set of ROM instructions, thereby securely patching the ROM code.

Abstract: A secure read-only-memory (ROM) code patching system includes a processor that is configured to generate first partial cryptographic data based on a ROM patch and a set of secret bits, and authenticate the ROM patch based on a match between the first partial cryptographic data and reference partial cryptographic data of the ROM patch. Upon the authentication of the ROM patch, the processor is further configured to generate an address associated with a set of ROM instructions of a ROM code. Based on a match between the generated address and a ROM patch address of the ROM patch, the processor is further configured to execute a set of patch instructions of the ROM patch that is successfully authenticated instead of the set of ROM instructions, thereby securely patching the ROM code.