Abstract: A method and a system for reducing delay noise in an integrated circuit (IC) includes generating delay information for each net, and each device of the IC. Each net has a ground capacitance, a coupling capacitance, and a resistance. An effective capacitance is computed for each net. The effective capacitance is divided by sum of the ground capacitance and the coupling capacitance to compute a scale factor. The effective capacitance is then scaled by the scale factor to determine a delay noise induced load. Finally, the timing paths are optimized incrementally by using the delay noise induced load, the resistance, and the delay information.

Abstract: A method and a system for reducing delay noise in an integrated circuit (IC) includes generating delay information for each net, and each device of the IC. Each net has a ground capacitance, a coupling capacitance, and a resistance. An effective capacitance is computed for each net. The effective capacitance is divided by sum of the ground capacitance and the coupling capacitance to compute a scale factor. The effective capacitance is then scaled by the scale factor to determine a delay noise induced load. Finally, the timing paths are optimized incrementally by using the delay noise induced load, the resistance, and the delay information.