Patents by Inventor Atul K. Jain

Atul K. Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Timing closure for system on a chip using voltage drop based standard delay formats
    Patent number: 7324914
    Abstract: A timing closure analysis associated with SoCs uses voltage drop based standard delay formats (SDFs). Static timing analysis (STA) is implemented using multiple SDFs, one for each mode (ATPG Test, BIST Test, Functional) as contrasted with doing STA with only one worst-case SDF for all modes. The multiple SDFs account for the impact of dynamic voltage drops on delays in addition to static IR drops.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: January 29, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Atul K. Jain, Venugopal Puvvada, Jayashree Saxena
  • Power reduction in module-based scan testing
    Publication number: 20020170010
    Abstract: A circuit and method for reducing the power consumed by module-based scan testing. In one embodiment constant data is provided to inputs, such as 33, of scan chains not used in testing, such as 32. Another embodiment is a method whereby transitions in a subset of scan chains, such as 32, are minimized through the use of constant input data.
    Type: Application
    Filed: April 24, 2002
    Publication date: November 14, 2002
    Inventors: Jayashree Saxena, Kenneth M. Butler, Atul K. Jain, Anthony Fryars, Graham G. Hetherington