Abstract: Disclosed approaches for processing a circuit design targeted to a programmable integrated circuit (IC) include inputting the circuit design to a programmed processor. Each path of the circuit design specifies a plurality of circuit elements of the programmable IC. For each circuit element specified in a path of the plurality of paths the processor looks up in a memory a mean delay associated with the circuit element, looks up a sigma factor associated with the circuit element, and looks up a delta factor associated with the circuit element. The processor determines a delay of the path as a function of the mean delay, sigma factor, and delta factor of each circuit element in the path.

Abstract: Methods and systems are disclosed for placement and routing of a circuit design. A set of timing constraints is retrieved that specifies timing for objects included in a first shell circuit design configured to provide an interface for communication between the circuit design and the set of dedicated hardware resources on an IC. One or more objects of the first shell circuit design that do not affect timing of the circuit design are identified and removed from the first shell circuit design to produce a second shell circuit design. The circuit design is placed and routed according to timing constraints specified for objects of the first shell circuit design that are included in the second shell circuit design. The placed and routed circuit design is stored in a memory circuit.

Abstract: Approaches for processing a circuit design include determining pin slack values for pins of the circuit elements in the circuit design. A processor selects a subset of endpoints based on pin slack values of the endpoints being in a critical slack range and determines startpoints of the circuit design that are in respective critical fanin cones. For each endpoint of the subset, the processor determines an arrival time from each startpoint in the respective critical fanin cone and determines for each startpoint-endpoint pair, a respective set of constraint values as a function of the respective arrival time from the startpoint. The processor generates a graph in the memory circuit from the startpoint-endpoint pairs. First nodes in the graph represent the startpoints and second nodes in the graph represent the endpoints, and values in the respective set of constraint values are associated with edges that connect the nodes.

Abstract: Determining delays of paths in a circuit design includes determining whether or not each path of the plurality of paths matches a path definition of a plurality of path definitions in a path database. For each path that matches a path definition, a first path delay value associated with the matching path definition is read from the path database and associated with the matching path of the circuit design. For each path that does not match any of the path definitions, respective element delay values of elements of the path are read from an element database. A second path delay value of the non-matching path is computed as a function of the respective element delay values, and the second path delay value is associated with the path. The first and second path delay values are output along with information indicating the associated paths.

Abstract: A method and apparatus are presented that can analyze the performance of an integrated circuit design at multiple corners, under multiple modes, and for multiple objectives efficiently and simultaneously. The extraction, timing analysis, and optimization functions are integrated into a mechanism that provides a novel problem formulation. A plurality of virtual timing graphs are maintained and updated simultaneously by providing a data structure that can efficiently store operating data for an arbitrary number of conditions at each node. This data structure is populated according to the design, and as optimizations are made, the operating data for all design conditions is updated simultaneously. Timing violations can be reported across all corners and modes. By integrating this multi-corner multi-mode analysis with circuit optimization, a convergent mechanism is provided. In this way, design constraints are evaluated simultaneously for an arbitrary number of design conditions.