Abstract: In one embodiment, a method includes initiating cluster parameters that govern how a non-volatile memory (NVM) cluster functions and operates. Submission and completion queues of shared NVM on other nodes in the NVM cluster are mapped based on details of the shared NVM on the other nodes in the NVM cluster. The submission queue is configured to store commands to access the shared NVM according to a first-in-first-out (FIFO) scheme. The completion queue is configured to store completed commands after being processed through the submission queue. In another embodiment, a host-based data storage system includes NVM configured to store data. The host-based data storage system further includes a processor and logic integrated with and/or executable by the processor to perform the foregoing method.

Abstract: In one embodiment, a method includes initiating cluster parameters that govern how a non-volatile memory (NVM) cluster functions and operates. Submission and completion queues of shared NVM on other nodes in the NVM cluster are mapped based on details of the shared NVM on the other nodes in the NVM cluster. The submission queue is configured to store commands to access the shared NVM according to a first-in-first-out (FIFO) scheme. The completion queue is configured to store completed commands after being processed through the submission queue. In another embodiment, a host-based data storage system includes NVM configured to store data. The host-based data storage system further includes a processor and logic integrated with and/or executable by the processor to perform the foregoing method.

Abstract: In one embodiment, a system includes non-volatile memory (NVM) configured to store data, a memory controller connected to the NVM via a NVM interface, a network interface card (NIC) connected to the memory controller, a processor, the logic being configured to: initiate cluster parameters that govern how a NVM cluster will function and operate, multicast cluster parameters of the NVM cluster at predetermined intervals to any other node in the NVM cluster, and map submission and completion queues of any shared NVM on other nodes in the NVM cluster to the memory controller based on details of the shared NVM on the other nodes in the NVM cluster, wherein the submission queue is configured to store commands to access the shared NVM and the completion queue is configured to store completed commands after being processed through the submission queue.

Abstract: In one embodiment, a method includes sending a switch discovery signal to one or more of a plurality of switches, receiving a reply to the switch discovery signal from the one or more of the plurality of switches, each reply comprising a switch identifier (ID) and a quantity of ports, receiving configuration information identifying at least one virtual stack to create, determining a virtual topology for the at least one virtual stack based on the configuration information, creating a first virtual stack of the at least one virtual stack by assigning at least one switch port of a source switch to the first virtual stack of the at least one virtual stack in accordance with the configuration information, and storing the virtual topology in a mapping table local to a computer comprising the first computer processor.

Abstract: In one embodiment, a method includes sending a switch discovery signal to one or more of a plurality of switches, receiving a reply to the switch discovery signal from the one or more of the plurality of switches, each reply comprising a switch identifier (ID) and a quantity of ports, receiving configuration information identifying at least one virtual stack to create, determining a virtual topology for the at least one virtual stack based on the configuration information, creating a first virtual stack of the at least one virtual stack by assigning at least one switch port of a source switch to the first virtual stack of the at least one virtual stack in accordance with the configuration information, and storing the virtual topology in a mapping table local to a computer comprising the first computer processor.

Abstract: A first processor assigns switches and/or switch ports to a virtual stack according to configuration information and stores the virtual topography of the virtual stack in a mapping table. The mapping table correlates switches, switch ports, computer processors, and virtual stacks. The first processor receives a data unit from a first switch that includes a source address and a destination address. The destination address identifies a switch and switch port. The first processor compares the destination address to the mapping table to determine a second computer processor and sends the data unit to the second computer processor, the second computer processor corresponding to a switch and/or switch port identified in the destination address of the data unit.

Abstract: In one embodiment, a system includes non-volatile memory (NVM) configured to store data, a memory controller connected to the NVM via a NVM interface, a network interface card (NIC) connected to the memory controller, a processor, the logic being configured to: initiate cluster parameters that govern how a NVM cluster will function and operate, multicast cluster parameters of the NVM cluster at predetermined intervals to any other node in the NVM cluster, and map submission and completion queues of any shared NVM on other nodes in the NVM cluster to the memory controller based on details of the shared NVM on the other nodes in the NVM cluster, wherein the submission queue is configured to store commands to access the shared NVM and the completion queue is configured to store completed commands after being processed through the submission queue.

Abstract: A scaled-out fabric coupler (SFC) chassis includes a plurality of root fabric cards installed on the one side of the SFC chassis. Each root fabric card has a plurality of electrical connectors. A plurality of line cards is installed on the opposite side of the SFC chassis. Each line card is one of two types of line cards. One of the two types of line cards is a switch-based network line card having network ports for connecting to servers and switches. The other of the two types of line cards is a leaf fabric card having fabric ports for connecting to a fabric port of a network element. Each of the two types of the line cards has electrical connectors that mate with one electrical connector of each root fabric card installed in the chassis.

Abstract: A first processor assigns switches and/or switch ports to a virtual stack according to configuration information and stores the virtual topography of the virtual stack in a mapping table. The mapping table correlates switches, switch ports, computer processors, and virtual stacks. The first processor receives a data unit from a first switch that includes a source address and a destination address. The destination address identifies a switch and switch port. The first processor compares the destination address to the mapping table to determine a second computer processor and sends the data unit to the second computer processor, the second computer processor corresponding to a switch and/or switch port identified in the destination address of the data unit.

Abstract: A system includes scaled-out fabric coupler (SFC) boxes and distributed line card (DLC) boxes. Each SFC box has fabric ports and a cell-based switch fabric for switching cells. Each DLC box is in communication with every SFC box. Each DLC box has network ports receiving packets and network processors. Each processor has a fabric interface that provides SerDes channels. The processors divide each packet received over the network ports into cells and distribute the cells of each packet across the SerDes channels. Each DLC box further comprises DLC fabric ports through which the DLC is in communication with the SFCs. Each DLC fabric port includes a pluggable interface with a given number of lanes over which to transmit and receive cells. Each lane is mapped to one of the SerDes channels such that an equal number of SerDes channels of each fabric interface is mapped to each DLC fabric port.

Abstract: A first conduit is externally attached to one of two opposing sidewalls of electronic equipment and a second conduit is externally attached to the other of the opposing sidewalls. Each conduit has an open end, a closed end, and a side having a vent that is aligned with a vent in the sidewall of the electronic equipment to which that conduit is attached. The first conduit takes air in through its open end, channels the air in a direction substantially orthogonal to the direction of air flowing through the electronic equipment, and directs the air into the electronic equipment through its aligned vents. The second conduit receives air from the electronic equipment through its aligned vents, channels the air in a direction that is substantially orthogonal to the direction of air flowing through the electronic equipment, and exhausts the air through the open end of the second conduit.

Abstract: A scaled-out fabric coupler (SFC) chassis includes a plurality of root fabric cards installed on the one side of the SFC chassis. Each root fabric card has a plurality of electrical connectors. A plurality of line cards is installed on the opposite side of the SFC chassis. Each line card is one of two types of line cards. One of the two types of line cards is a switch-based network line card having network ports for connecting to servers and switches. The other of the two types of line cards is a leaf fabric card having fabric ports for connecting to a fabric port of a network element. Each of the two types of the line cards has electrical connectors that mate with one electrical connector of each root fabric card installed in the chassis.

Abstract: A system includes scaled-out fabric coupler (SFC) boxes and distributed line card (DLC) boxes. Each SFC box has fabric ports and a cell-based switch fabric for switching cells. Each DLC box is in communication with every SFC box. Each DLC box has network ports receiving packets and network processors. Each processor has a fabric interface that provides SerDes channels. The processors divide each packet received over the network ports into cells and distribute the cells of each packet across the SerDes channels. Each DLC box further comprises DLC fabric ports through which the DLC is in communication with the SFCs. Each DLC fabric port includes a pluggable interface with a given number of lanes over which to transmit and receive cells. Each lane is mapped to one of the SerDes channels such that an equal number of SerDes channels of each fabric interface is mapped to each DLC fabric port.

Abstract: A first conduit is externally attached to one of two opposing sidewalls of electronic equipment and a second conduit is externally attached to the other of the opposing sidewalls. Each conduit has an open end, a closed end, and a side having a vent that is aligned with a vent in the sidewall of the electronic equipment to which that conduit is attached. The first conduit takes air in through its open end, channels the air in a direction substantially orthogonal to the direction of air flowing through the electronic equipment, and directs the air into the electronic equipment through its aligned vents. The second conduit receives air from the electronic equipment through its aligned vents, channels the air in a direction that is substantially orthogonal to the direction of air flowing through the electronic equipment, and exhausts the air through the open end of the second conduit.

Abstract: A first conduit is externally attached to one of two opposing sidewalls of electronic equipment and a second conduit is externally attached to the other of the opposing sidewalls. Each conduit has an open end, a closed end, and a side having a vent that is aligned with a vent in the sidewall of the electronic equipment to which that conduit is attached. The first conduit takes air in through its open end, channels the air in a direction substantially orthogonal to the direction of air flowing through the electronic equipment, and directs the air into the electronic equipment through its aligned vents. The second conduit receives air from the electronic equipment through its aligned vents, channels the air in a direction that is substantially orthogonal to the direction of air flowing through the electronic equipment, and exhausts the air through the open end of the second conduit.

Abstract: A first conduit is externally attached to one of two opposing sidewalls of electronic equipment and a second conduit is externally attached to the other of the opposing sidewalls. Each conduit has an open end, a closed end, and a side having a vent that is aligned with a vent in the sidewall of the electronic equipment to which that conduit is attached. The first conduit takes air in through its open end, channels the air in a direction substantially orthogonal to the direction of air flowing through the electronic equipment, and directs the air into the electronic equipment through its aligned vents. The second conduit receives air from the electronic equipment through its aligned vents, channels the air in a direction that is substantially orthogonal to the direction of air flowing through the electronic equipment, and exhausts the air through the open end of the second conduit.

Abstract: A plurality of channels of a wavelength division multiplexing system may be subjected to dispersion compensation in a fashion which enables tuning of the compensation for each individual wavelength channel. Moreover, the tuning may be done in a space-efficient fashion. The chirped Bragg gratings may be formed, for example, on a planar light circuit. Each grating may be heated to controllably adjust its dispersion compensation, in one embodiment of the present invention.

Abstract: A plurality of channels of a wavelength division multiplexing system may be subjected to dispersion compensation in a fashion which enables tuning of the compensation for each individual wavelength channel. Moreover, the tuning may be done in a space-efficient fashion. The chirped Bragg gratings may be formed, for example, on a planar light circuit. Each grating may be heated to controllably adjust its dispersion compensation, in one embodiment of the present invention.

Abstract: A visual indication of the location and duration of a measurement gate relative to the signal being measured is provided on a display. In response to a start gate signal measurements are initiated and a predetermined change is effected in the normally displayed visual indication of the signal being measured. In response to a gate close indication, measurements are terminated and the normally displayed visual indication is resumed. The normal and changed visual indications are effected by a display control signal produced by summing the signal to be measured and an event gate signal at a point in the circuit near where the event gate signal is generated.

Abstract: A method of digitally controlling the gate for a timing counter, to open and close the gate based on the occurrence of signal events, rather than on the envelope of the pulse. In a particular embodiment, a digital divider controls the gate, so that, when a pulse burst of RF is encountered, the gate opens on the second signal event. The divider can be programmed to close the gate any number of signal events later. Measurements are taken for an integral number of signal events, while counting time events from a precision clock. A series of measurements can be taken with various integral numbers of signal events for frequency profiling. By incrementing the digital divider from n to n+1 signal events for successive measurements, and subtracting the results, very narrow gates are effectively generated which move through the pulse cycle by cycle for frequency profiling.