Patents by Inventor AtulKumar KASHYAP

AtulKumar KASHYAP has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus having error detection in sequential logic
    Patent number: 8624623
    Abstract: According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: January 7, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Navneet Gupta, Prashant Dubey, Kaushik Saha, AtulKumar Kashyap
  • APPARATUS
    Publication number: 20130169360
    Abstract: According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Applicant: STMICROELECTRONICS PVT. LTD.
    Inventors: Navneet GUPTA, Prashant DUBEY, Kaushik SAHA, AtulKumar KASHYAP