Abstract: A transfer circuit for signal lines comprises a bipolar transistor and two MIS transistors. A base of the bipolar transistor is connected to a first line of the signal lines, a collector of the bipolar transistor is connected to a power source, the two MIS transistors are connected in series, the connected point is connected to an emitter of the bipolar transistor, and one end of the series-connected MIS transistors is connected to the first line and the other end is connected to a second line of the signal lines. When the first line is transferred to the second line, the MIS transistor connected between the base and emitter of the bipolar transistor is made non-conductive and the other MIS transistor connected to the second line is made conductive. The transfer circuit constituted as above can carry out the transfer of the signal lines at a high speed by rapidly charging the second line.

Abstract: A semiconductor memory device includes a reset circuit for equalizing potentials of a pair of signal lines for transferring a complementary signal, and a clock generating circuit generating a first clock signal and a second clock signal at a time different from the generation of the first clock. A logical OR gate circuit generates a reset signal based on the first and second clock signals.When the pulse width of an active low chip selection signal is shorter than a predetermined time period, the pulse width of the reset signal is made longer than that generated when the pulse width of the signal is longer than the predetermined time period. As a result, the potentials of a pair of complementary bit lines connected to each cell in the memory cell array can be reliably reset, and the delay time in the access operation can be reduced.

Abstract: A sensor amplifier of a differential amplifier type having an input selecting function. The sense amplifier has a pair of input circuit portions receiving a plurality of pairs of complementary input signals, one of the input circuit portions has a plurality of circuit units each generating the amplified output of one of a pair of complementary input signals in response to an address signal applied thereto, and the other input circuit portion comprising a plurality of circuit units each generating the amplified output of the other one of the pair of complementary input signals in response to the address signal applied thereto, The sense amplifier selects one of a plurality of pairs of complementary input signals, i.e., complementary signals on bit lines or on data buses, in accordance with the address signal and generates an output signal corresponding to a selected pair of complementary input signals.

Abstract: A sense amplifier comprising two asymmetrical differential amplifiers connected to each other in such a way that their outputs are accelerated to charge up one another by utilizing nodes at which potentials are changed in response to a change of the input signal supplied from a pair of bit lines or a pair of data lines, whereby the operating speed of the sense amplifier is increased.