Abstract: An arithmetic processing device includes: a decoding circuit configured to decode a command; a command execution circuit configured to execute the command decoded by the decoding circuit; a register circuit configured to include a plurality of registers for holding data used by the command execution circuit; an identification information holding circuit configured to store identification information for identifying a register for writing a specific value when the command is a register writing command; a setting circuit configured to hold the specific value; and an operation control circuit configured to execute inhibiting processing when the command is a register reading command, the inhibiting processing including inhibiting an access of the register by the register reading command and selecting the specific value held in the setting circuit.

Abstract: A processing device includes an instruction decode circuit including decoders that decode instructions respectively assigned an instruction number that is determined for every one of the decoders, an instruction execution circuit that executes the instructions decoded by the instruction decode circuit, an instruction complete holding circuit including hold blocks provided in correspondence with each of the decoders and respectively including hold regions assigned the instruction number, and used for an instruction complete process, and an instruction complete controller that stores instruction information that is generated by decoding the instructions by the decoders, in one of the hold regions of the hold block corresponding to the decoder that decodes the instruction, based on the instruction number, and obtain, in order, the instruction information corresponding to the instructions executed by the instruction execution circuit from the instruction complete holding circuit, to perform the instruction comple

Abstract: An arithmetic circuit performs a floating-point operation. A floating-point register includes entries each allocated to an architectural register or a renaming register. An operation execution controller circuit issues a floating-point operation instruction and outputs a termination report of the floating-point operation before the floating-point operation is terminated. When exception handling is not performed at the time of instruction completion even when an exception is detected in the operation of the floating-point operation instruction, an instruction completion controller circuit outputs a release instruction that indicates a release of a renaming register when instruction execution is completed after the termination report is received.

Abstract: A processing device includes an instruction decode circuit including decoders that decode instructions respectively assigned an instruction number that is determined for every one of the decoders, an instruction execution circuit that executes the instructions decoded by the instruction decode circuit, an instruction complete holding circuit including hold blocks provided in correspondence with each of the decoders and respectively including hold regions assigned the instruction number, and used for an instruction complete process, and an instruction complete controller that stores instruction information that is generated by decoding the instructions by the decoders, in one of the hold regions of the hold block corresponding to the decoder that decodes the instruction, based on the instruction number, and obtain, in order, the instruction information corresponding to the instructions executed by the instruction execution circuit from the instruction complete holding circuit, to perform the instruction comple

Abstract: An arithmetic processing device includes: a decoding circuit configured to decode a command; a command execution circuit configured to execute the command decoded by the decoding circuit; a register circuit configured to include a plurality of registers for holding data used by the command execution circuit; an identification information holding circuit configured to store identification information for identifying a register for writing a specific value when the command is a register writing command; a setting circuit configured to hold the specific value; and an operation control circuit configured to execute inhibiting processing when the command is a register reading command, the inhibiting processing including inhibiting an access of the register by the register reading command and selecting the specific value held in the setting circuit.

Abstract: An arithmetic circuit performs a floating-point operation. A floating-point register includes entries each allocated to an architectural register or a renaming register. An operation execution controller circuit issues a floating-point operation instruction and outputs a termination report of the floating-point operation before the floating-point operation is terminated. When exception handling is not performed at the time of instruction completion even when an exception is detected in the operation of the floating-point operation instruction, an instruction completion controller circuit outputs a release instruction that indicates a release of a renaming register when instruction execution is completed after the termination report is received.

Abstract: An arithmetic processing unit including a branch instruction execution management unit configured to accumulate a branch instruction waiting to be executed and to manage completion of a branch instruction, a completion processing waiting storage unit configured to accumulate an identifier of an instruction waiting for completion processing according to an execution sequence of a program, a completion processing unit configured to activate resource update processing due to execution of a branch instruction when the completion processing unit receives an execution completion report for the branch instruction from the branch instruction execution management unit and identified by the identifier, and a promotion unit configured to, when an identifier accumulated at the top of the completion processing waiting storage unit indicates a branch instruction, cause the completion processing unit to activate the resource update processing without waiting for the execution completion report for the branch instruction.