Abstract: A non-destructive test structure for printed circuit board characterization and method of testing the same are disclosed. In one form, a method for testing a printed circuit board can include applying a test signal to a first test location of a first test structure associated with a first inner bus layer of a printed circuit board. The method can also include measuring a crosstalk voltage at a second test location operably associated with the first test structure. The method can further include comparing the crosstalk voltage to a crosstalk specification of the printed circuit, board.

Abstract: A non-destructive test structure for printed circuit board characterization and method of testing the same are disclosed. In one form, a method for testing a printed circuit board can include applying a test signal to a first test location of a first test structure associated with a first inner bus layer of a printed circuit board. The method can also include measuring a crosstalk voltage at a second test location operably associated with the first test structure. The method can further include comparing the crosstalk voltage to a crosstalk specification of the printed circuit, board.

Abstract: Testing of a printed circuit board (PCB) impedance measurement region is performed using time domain reflectometry (TDR) that measures reflections and time delays of pulses injected into an impedance measurement region (impedance coupon). Timing markers are used to give both visual and electrical indications of precisely where the desired impedance measurement region (impedance coupon) begins and ends. The timing markers are placed on either end of the impedance coupon to be measured and give explicit start and end points to the PCB impedance measurement region. The timing markers may be in any form which has a discernable impedance difference from the PCB impedance measurement region.

Abstract: Testing of a printed circuit board (PCB) impedance measurement region is performed using time domain reflectometry (TDR) that measures reflections and time delays of pulses injected into an impedance measurement region (impedance coupon). Timing markers are used to give both visual and electrical indications of precisely where the desired impedance measurement region (impedance coupon) begins and ends. The timing markers are placed on either end of the impedance coupon to be measured and give explicit start and end points to the PCB impedance measurement region. The timing markers may be in any form which has a discernable impedance difference from the PCB impedance measurement region.

Abstract: Flip-chip is fast becoming the mounting method of choice in the semiconductor industry for dice having a high number of contacts. Since many applications require known-good-die, these flip-chip semiconductor dice must be tested and burned-in. By testing and burning-in the semiconductor wafers prior to solder bumping, the probe tips (42, 44, 46 & 48) can contact the hard planar surface of the under-bump-metallurgy (40) on each bonding pad (14) for easier and more reliable contact and hence test results. The probe tips can be either of an array (42 & 44) or cantilevered needle (46 & 48) type. Blunt probe tips (42 & 48) are well-suited to making contact on the shoulder of each bonding pad of each semiconductor die, while sharp probe tips (44 & 46) are preferable for contacting the center of each bonding pad. Solder bumping is performed post-testing.

Abstract: A single metal-plate bypass capacitor (10) includes a metal top plate (26) separated from a silicon substrate (12) by a thermally-grown, silicon dioxide dielectric (16) layer. An additional silicon plate (36) can be included intermediate to the metal top plate (26) and the silicon substrate (12) for multiple power supply devices. The silicon substrate (12) is electrically accessed through a metal contact pad (28) overlying a doped region (34) of the silicon substrate (12). The metal contact pad (28) is electrically isolated from the top plate (26) by an isolation structure (30). The bypass capacitor (10) is designed to be attached directly to the top surface of a semiconductor device (18), which enables the bypass capacitor (10) to be interconnected to the semiconductor device (18) by a plurality of bonding wires (25) having a minimal length. Because the capacitor dielectric (16) is formed as a very thin layer by the thermal oxidation of silicon, the self-inductance of bypass capacitor (10) is minimized.

Abstract: A semiconductor device (10) includes a voltage distribution ring (20) attached to a plurality of leads (16). The ring is made up of an insulating layer (24), preferably polyimide, and a metal layer (22), preferably gold-plated copper foil. The ring may also include intervening adhesive layers (not illustrated). The ring surrounds a semiconductor die (12) and is electrically coupled to bond pads (14) of the die by wire bond (18). In various embodiment of the invention, the ring may be segmented to distribute two different voltages, such as power and ground; the ring may include slots to expose underlying portions of the leads; and the ring may be attached to either the top surface or bottom surface of the leads.