Patents by Inventor Audrey Hsiao-Chiu HSU

Audrey Hsiao-Chiu HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10468257
    Abstract: Semiconductor device structures and methods for forming the same are provided. The method for forming a semiconductor device structure includes forming a dummy gate structure over a substrate and forming a dielectric layer over the substrate around the dummy gate structure. The method for forming a semiconductor device structure further includes removing the dummy gate structure and removing a portion of the dielectric layer to form a funnel shaped trench. The method for forming a semiconductor device structure further includes forming a gate structure in a bottom portion of the funnel shaped trench and filling a hard mask material in a top portion of the funnel shaped trench to form a funnel shaped hard mask structure.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Shih-Wen Liu, Audrey Hsiao-Chiu Hsu
  • Patent number: 10276437
    Abstract: A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Audrey Hsiao-Chiu Hsu, Fu-Kai Yang, Mei-Yun Wang, Hsien-Cheng Wang, Shih-Wen Liu, Hsin-Ying Lin
  • Publication number: 20170103918
    Abstract: A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.
    Type: Application
    Filed: December 20, 2016
    Publication date: April 13, 2017
    Inventors: Audrey Hsiao-Chiu Hsu, Fu-Kai Yang, Mei-Yun Wang, Hsien-Cheng Wang, Shih-Wen Liu, Hsin-Ying Lin
  • Patent number: 9576847
    Abstract: Methods for forming integrated circuit structures are provided. The method includes providing a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The method further includes forming a gate structure over the substrate and forming an inter-layer dielectric (ILD) layer over the substrate. The method further includes forming a cutting mask over a portion of the gate structure over the isolation structure, and the cutting mask has an extending portion covering a portion of the ILD layer. The method further includes forming a photoresist layer having an opening, and a portion of the extending portion of the cutting mask is exposed by the opening. The method further includes etching the ILD layer through the opening to form a trench and filling the trench with a conductive material to form a contact.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Shih-Wen Liu, Fu-Kai Yang, Audrey Hsiao-Chiu Hsu
  • Patent number: 9536754
    Abstract: A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Audrey Hsiao-Chiu Hsu, Fu-Kai Yang, Mei-Yun Wang, Hsien-Cheng Wang, Shih-Wen Liu, Hsin-Ying Lin
  • Publication number: 20160358779
    Abstract: Semiconductor device structures and methods for forming the same are provided. The method for forming a semiconductor device structure includes forming a dummy gate structure over a substrate and forming a dielectric layer over the substrate around the dummy gate structure. The method for forming a semiconductor device structure further includes removing the dummy gate structure and removing a portion of the dielectric layer to form a funnel shaped trench. The method for forming a semiconductor device structure further includes forming a gate structure in a bottom portion of the funnel shaped trench and filling a hard mask material in a top portion of the funnel shaped trench to form a funnel shaped hard mask structure.
    Type: Application
    Filed: August 18, 2016
    Publication date: December 8, 2016
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Ying LIN, Mei-Yun WANG, Hsien-Cheng WANG, Fu-Kai YANG, Shih-Wen LIU, Audrey Hsiao-Chiu HSU
  • Patent number: 9425048
    Abstract: Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor device structure further includes a funnel shaped hard mask structure formed over the metal gate structure. Formation of voids, which tend to be formed in a rectangular hard mask structure, is prevented. In addition, formation of a self-aligned contact in the semiconductor device becomes easier, and risks of shortage between the contact and a metal gate structure in the semiconductor device decreased. In addition, a method for forming the semiconductor device structure is also provided. The method may include a gate last process.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: August 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Shih-Wen Liu, Audrey Hsiao-Chiu Hsu
  • Publication number: 20160211176
    Abstract: Methods for forming integrated circuit structures are provided. The method includes providing a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The method further includes forming a gate structure over the substrate and forming an inter-layer dielectric (ILD) layer over the substrate. The method further includes forming a cutting mask over a portion of the gate structure over the isolation structure, and the cutting mask has an extending portion covering a portion of the ILD layer. The method further includes forming a photoresist layer having an opening, and a portion of the extending portion of the cutting mask is exposed by the opening. The method further includes etching the ILD layer through the opening to form a trench and filling the trench with a conductive material to form a contact.
    Type: Application
    Filed: March 25, 2016
    Publication date: July 21, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Ying LIN, Mei-Yun WANG, Hsien-Cheng WANG, Shih-Wen LIU, Fu-Kai YANG, Audrey Hsiao-Chiu HSU
  • Patent number: 9312259
    Abstract: Embodiments of mechanism for an integrated circuit (IC) structure are provided. The IC structure includes a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The IC structure further includes a gate structure formed over the substrate, and the gate structure extends from the first diffusion region to the second diffusion region. The IC structure further includes a contact formed over the substrate, and the contact includes a wide portion over the first diffusion region and the second diffusion region and a thin portion over the isolation structure.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: April 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Shih-Wen Liu, Fu-Kai Yang, Audrey Hsiao-Chiu Hsu
  • Patent number: 9299657
    Abstract: A method for manufacturing semiconductor device is provided. The method includes the following operations: providing a first conductive portion, a second conductive portion and a third conductive portion over a substrate; forming a dielectric layer over the first conductive portion, the second conductive portion, and the third conductive portion; forming a high-resistance layer over the first conductive portion; forming an oxide layer over the high-resistance layer and the dielectric layer; patterning the dielectric layer and the oxide layer by using the high-resistance layer as a blocking layer to form a first recess to expose the second conductive portion and the third conductive portion and to prevent the first conductive portion from exposure; and forming a plug layer in the first recess to connect the second conductive portion and the third conductive portion.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: March 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Audrey Hsiao-Chiu Hsu, Fu-Kai Yang, Mei-Yun Wang, Hsien-Cheng Wang, Shih-Wen Liu, Hsin-Ying Lin
  • Publication number: 20150380270
    Abstract: A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.
    Type: Application
    Filed: August 31, 2015
    Publication date: December 31, 2015
    Inventors: AUDREY HSIAO-CHIU HSU, FU-KAI YANG, MEI-YUN WANG, HSIEN-CHENG WANG, SHIH-WEN LIU, HSIN-YING LIN
  • Patent number: 9123563
    Abstract: A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Audrey Hsiao-Chiu Hsu, Fu-Kai Yang, Mei-Yun Wang, Hsien-Cheng Wang, Shih-Wen Liu, Hsin-Ying Lin
  • Publication number: 20150206872
    Abstract: A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 23, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: AUDREY HSIAO-CHIU HSU, FU-KAI YANG, MEI-YUN WANG, HSIEN-CHENG WANG, SHIH-WEN LIU, HSIN-YING LIN
  • Publication number: 20150179573
    Abstract: A method for manufacturing semiconductor device is provided. The method includes the following operations: providing a first conductive portion, a second conductive portion and a third conductive portion over a substrate; forming a dielectric layer over the first conductive portion, the second conductive portion, and the third conductive portion; forming a high-resistance layer over the first conductive portion; forming an oxide layer over the high-resistance layer and the dielectric layer; patterning the dielectric layer and the oxide layer by using the high-resistance layer as a blocking layer to form a first recess to expose the second conductive portion and the third conductive portion and to prevent the first conductive portion from exposure; and forming a plug layer in the first recess to connect the second conductive portion and the third conductive portion.
    Type: Application
    Filed: December 24, 2013
    Publication date: June 25, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: AUDREY HSIAO-CHIU HSU, FU-KAI YANG, MEI-YUN WANG, HSIEN-CHENG WANG, SHIH-WEN LIU, HSIN-YING LIN
  • Publication number: 20150123213
    Abstract: Embodiments of mechanism for an integrated circuit (IC) structure are provided. The IC structure includes a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The IC structure further includes a gate structure formed over the substrate, and the gate structure extends from the first diffusion region to the second diffusion region. The IC structure further includes a contact formed over the substrate, and the contact includes a wide portion over the first diffusion region and the second diffusion region and a thin portion over the isolation structure.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Hsin-Ying LIN, Mei-Yun WANG, Hsien-Cheng WANG, Shih-Wen LIU, Fu-Kai YANG, Audrey Hsiao-Chiu HSU
  • Publication number: 20150123175
    Abstract: Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor device structure further includes a funnel shaped hard mask structure formed over the metal gate structure. In addition, a method for forming the semiconductor device structure is also provided.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Ying LIN, Mei-Yun WANG, Hsien-Cheng WANG, Fu-Kai YANG, Shih-Wen LIU, Audrey Hsiao-Chiu HSU